Events - 2021

Candidate: Ian Elmor Lang
Title: Worst-Case Latency Analysis for the Versal Network-on-Chip
Date: December 16, 2021
Time: 15:00
Place: online
Supervisor(s): Kapre, Nachiket - Pellizzoni, Rodolfo

Abstract:
The recent line of Versal FPGA devices from Xilinx Inc. includes a hard NetworkOn-Chip (NoC) embedded in the programmable logic,
designed to be a high-performance system-level interconnect. While the target markets for Versal devices include applications

Candidate: Bianca Esanu
Title: An Assessment of, and Improvements to, the Digital Forensics Acquisition Process of a Law Enforcement Agency
Date: December 10, 2021
Time: 13:00
Place: MS Teams
Supervisor(s): Tripunitara, Mahesh

Abstract:
Forensics addresses the collection and analysis of evidence. Digital forensics is forensics in the context of digital devices. It
is a rapidly evolving field employed in various organizations such as law enforcement, government, and the private sector. The

Candidate: Srinirdheeshwar Kuttuva Prakash
Title: Managing HBM’s bandwidth in Multi-Die FPGAs using Overlay NoCs
Date: December 9, 2021
Time: 13:00
Place: online
Supervisor(s): Kapre, Nachiket - Patel, Hiren

Abstract:
We can improve HBM bandwidth distribution and utilization on a multi-die FPGA like Xilinx Alveo U280 by using Overlay
Network-on-Chips (NoCs). HBM in Xilinx Alveo U280 offers 8GBs of memory capacity with a theoretical maximum bandwidth of 460

Candidate: Xinyu Guo
Title: Degraded Reference Image Quality Assessment
Date: December 8, 2021
Time: 12:00
Place: MS Teams
Supervisor(s): Wang, Zhou

Abstract:
Images/videos are playing a more and more important role in the 21st century. The perceived quality of visual content often
degrades during the process of acquisition, storage, transmission, display and rendering. Since subjective evaluation of such a

Candidate: Di Wang
Title: Interval Type Inference: Improvements and Evaluations

Date: December 2, 2021
Time: 15:00
Place: MS Teams
Supervisor(s): Dietl, Werner

Abstract:
Interval analysis estimates the run-time intervals of numerical expressions in the source code by computing a lower bound and an
upper bound. Interval analysis for integral types is useful in providing facts of the target program to help developers find

Candidate: Harry Chan Chan
Title: Implementing FPGA-optimized Systolic Arrays using 2D Knapsack and Evolutionary Algorithms

Date: November 26, 2021
Time: 18:00
Place: MS Teams
Supervisor(s): Kapre, Nachiket

Abstract:
Underutilization of FPGA resources is a significant challenge in the deployment of FPGAs as neural network accelerators.
We propose an FPGA-optimized systolic array architecture to improve the CNN inference throughput by orders of magnitude through

Beginning September 23rd, and continuing every Thursday through this term, Dean Mary Wells will be available on the 1st floor of E7, outside the C&D, from 3-5 pm for a chat and to connect.

Beginning September 23rd, and continuing every Thursday through this term, Dean Mary Wells will be available on the 1st floor of E7, outside the C&D, from 3-5 pm for a chat and to connect.

Sustainable nanomaterials, such as cellulose nanocrystals (CNCs) are rod-like nanoparticles obtained by sulfuric acid hydrolysis of cellulose fibres.

Beginning September 23rd, and continuing every Thursday through this term, Dean Mary Wells will be available on the 1st floor of E7, outside the C&D, from 3-5 pm for a chat and to connect.