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DTSTART:20210314T070000
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DTSTART;TZID=America/Toronto:20211126T180000
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URL:https://uwaterloo.ca/electrical-computer-engineering/events/implementin
 g-fpga-optimized-systolic-arrays-using-2d
SUMMARY:Implementing FPGA-optimized Systolic Arrays using 2D Knapsack and\n
 Evolutionary Algorithms
CLASS:PUBLIC
DESCRIPTION:Candidate: Harry Chan Chan\nTitle: Implementing FPGA-optimized 
 Systolic Arrays using 2D Knapsack\nand Evolutionary Algorithms\n\nDate: No
 vember 26\, 2021\nTime: 18:00\nPlace: MS Teams\nSupervisor(s): Kapre\, Nac
 hiket\n\nABSTRACT:\nUnderutilization of FPGA resources is a significant ch
 allenge in the\ndeployment of FPGAs as neural network accelerators.\nWe pr
 opose an FPGA-optimized systolic array architecture to improve\nthe CNN in
 ference throughput by orders of magnitude through
DTSTAMP:20260413T082719Z
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