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DTSTART:20210314T070000
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DTSTART;TZID=America/Toronto:20211216T150000
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URL:https://uwaterloo.ca/electrical-computer-engineering/events/worst-case-
 latency-analysis-versal-network-chip
SUMMARY:Worst-Case Latency Analysis for the Versal Network-on-Chip
CLASS:PUBLIC
DESCRIPTION:Candidate: Ian Elmor Lang\nTitle: Worst-Case Latency Analysis f
 or the Versal Network-on-Chip\nDate: December 16\, 2021\nTime: 15:00\nPlac
 e: online\nSupervisor(s): Kapre\, Nachiket - Pellizzoni\, Rodolfo\n\nABSTR
 ACT:\nThe recent line of Versal FPGA devices from Xilinx Inc. includes a\n
 hard NetworkOn-Chip (NoC) embedded in the programmable logic\,\ndesigned t
 o be a high-performance system-level interconnect. While the\ntarget marke
 ts for Versal devices include applications
DTSTAMP:20260412T220726Z
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