Thursday, April 3, 2014 — 10:00 AM EDT

Candidate

Anirudh Mohan Kaushik

Title

Accelerating mixed-abstraction SystemC models using multi-core CPUs and GPUs

Supervisor

Patel, Hiren D.

Abstract

Functional validation is a critical part in the hardware design process cycle, and it contributes for nearly two-thirds of the overall development time. With increasing complexity of hardware designs and shrinking time-to-market constraints, the time and resources spent on functional validation has increased considerably. To mitigate the increasing cost of functional validation, research and academia have been engaged in proposing techniques for improving the simulation of hardware designs, which is a key technique used in the functional validation process. However, the proposed techniques for accelerating the simulation of hardware designs do not leverage the performance benefits offered by multi-core processors and heterogeneous processors available today. With the growing ubiquity of powerful heterogeneous computing systems, which integrate multi-core systems with heterogeneous processors such as GPUs, it is important to utilize these computing systems to address the functional validation bottleneck.

In this thesis, I propose a technique for accelerating SystemC simulations across multi-core CPUs and GPUs. In particular, I focus on accelerating simulation of SystemC models that are described at both the Register-Transfer Level (RTL) and Transaction Level (TL) abstractions.

The main contributions of this thesis are: a methodology for accelerating the simulation of mixed abstraction SystemC models defined at the RTL and TL abstractions on multi-core CPUs and GPUs, and an open-source static framework for parsing, analyzing, and performing source-to-source translation of identified portions of a SystemC model for execution on multi-core CPUs and GPUs.

Location 
EIT building
Room 3145

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