MachineFlow: A Web Tool to Adaptively Select EDA Tool Parameters for Digital ICs Using Statistical Learning
Siddharth Garg (Adjunct) and Hiren Patel
Digital integrated circuits (ICs) are the driving force behind computing, communication and entertainment in today's world. More powerful and energy efficient ICs continue to be designed and built by the semiconductor industry to meet current demands. In addition, complexity in Electronic Design Automation(EDA) software continues to grow to keep up with the design and technological advances in digital ICs. Design parameters that control various aspects of EDA software, such as synthesis, placement and routing settings, can affect the performance of ICs, and current standard cell logic synthesis and physical design flow tools consist of hundreds of such parameters to be specified by the designer. Discovering the optimal value for each parameter can result in significant performance and power efficiency gains. In this thesis, we develop a proof of concept web tool that uses open source EDA software to generate datasets for a large number of circuits and uses the data to build predictive models using statistical learning techniques. We use these models to select design parameters for the VLSI physical design flow floorplanning and placement stages that minimize the total wire-length of the integrated circuit. Using empirical evaluation on three real-world test circuits, we show a 15x-35x reduction in time spent to discover predicted values of one of the studied parameters that reduces total wire-length with statistical significance compared to a brute force exploration of the design space, with an error rate below 5%.
The key contributions of this thesis are:
- Development of a web based tool to perform VLSI physical design flow of a standard cell based integrated circuit, as well as generate and record data points at various stages of the flow to build predictive models.
- Development and investigation of predictive models through the web based tool, using the recorded data points and utilizing statistical learning techniques, to predict VLSI physical design flow floorplanning and placement tool parameters that minimize total wire-length in a particular integrated circuit.