Assem Shoukry Mohamed Hussein
Fault Tolerance of Stochastic Decoders
Mohamed Elmasry (Adjunct) and Vincent Gaudet
Low-density parity-check (LDPC) codes are very powerful linear error-correcting codes, first introduced by Gallager in 1963. Recently, they are being used in many communication standards due to their ability to achieve a near Shannon-capacity limit performance. Stochastic decoding has been emerging, since 2003, as an efficient method of iterative decoding of LDPC codes. In this work, we investigate the capability of stochastic decoding to tolerate circuit soft errors while maintaining good bit error rate performance and low error floor. Soft errors can be intended faults as a result of either VDD scaling to reduce power consumption or overclocking the system to achieve a higher throughput. They can also be unintended faults as a result of temperature or process variations.
We developed two models to emulate these circuit errors at the system level. We apply our models to two standardized LDPC codes (10GBASE-T and WiMAX). Simulation results show that stochastic decoding is very tolerant to faults and errors. Hence, stochastic decoding can be very useful in systems with very low power or high performance requirements where we can push the limits of power or speed by lowering VDD or highly overclocking the system while maintaining good performance. In addition, a chip has been designed and sent to fabrication to do post-silicon validation and verify our models.
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