FPGA Implementation of Clockless Stochastic LDPC Decoder
Channel coding is a technique used in digital communications to ensure a transmission is received across a noisy channel with minimal or no errors. This is done by adding redundant parity check bits to the signal prior to transmission to allow the decoder to reconstruct the original message at the receiver end. Low-Density Parity-Check (LDPC) codes are a powerful class of forward-error-correcting codes that perform at near the Shannon limit. Fully parallel implementations of LDPC decoders suffer from high wiring complexity and large clock networks leading to high power and area consumption.
Stochastic processing is a method of significantly reducing the wiring complexity. A stochastic signal is a serial stream of randomly generated bits used to convey a probability. The probability that each bit is '1' is equal to the probability that is being communicated. For example the probability 0.6 could be represented by the streams '10110' or '0110101011'. This type of probability representation simplifies multiplication and division operations into simple gates and so the iterative decoding algorithms simplify significantly. The disadvantage of stochastic decoding is that the decoding process is serial and so the throughput is reduced.
To allow for faster decoding speeds a clockless stochastic decoder is designed. With the absence of a large high-speed clock network the decoding throughput is not limited by clock delays. The decoding process is then allowed to continue in continuous time.
Proof of concept designs of (96,48) and (208,104) decoders are implemented on a Field-Programmable Logic Array (FPGA) from which frame error rate, throughput and power measurements are reported. Various trade-offs in the decoder design are explored.