Thursday, August 11, 2016 — 11:00 AM EDT

Candidate

Hassan Shakoor

Title

Fully Integrated 60 GHz Power Amplifiers in 45 nm SOI CMOS

Supervisor

Slim Boumaiza

Abstract

With the rapid growth of consumer demand for high data rates and high speed communications, the wireless spectrum has become increasingly precious. This has promoted the evolution of new standards and modulation schemes to improve spectral efficiency. The allocation of large bandwidths is an alternative to increase the channel capacity and data rate, however the availability of spectrum below 10 GHz is very limited. Recently, the 60 GHz spectrum has emerged as a potential candidate to support multi-Gb/s applications. It offers 7 GHz of unlicensed spectrum, for development of Wireless Personal Area Networks (WPAN) and cellular backhauls. Meanwhile, the scaling and advancement of low-cost complementary metal-oxide semiconductor (CMOS) technologies has enabled the use of CMOS devices at millimeter wave frequencies and the integration of analogue and digital circuitry has created platform for single chip radio development. However, low power density, low optimum load resistance and poor quality integrated passives (due to lossy silicon substrate) make CMOS technology a poor candidate for power amplifier (PA) design when, compared to silicon germanium and Group III-V technologies (gallium nitride, gallium arsenide and indium phosphide).

In order to overcome the above mentioned challenges in CMOS, this thesis re-explores FET-stacking as a power combining technique at 60 GHz using 45nm silicon-on-insulator (SOI) CMOS for millimeter-wave PAs. The stacking approach enables the use of higher supply voltages to obtain higher output power, and its higher load line resistance Ropt allows for the use of low impedance transformation matching networks. The reliability of CMOS PA under large signal operation is also addressed and improved with the FET-stacking approach applied in this work.

This thesis divides the millimeter-wave PA design problem in to two areas, active and passive, both of which are critically designed for optimum performance in terms of efficiency and output power while taking device and substrate parasitics into consideration. A transistor unit cell combination topology, the 'Manifold', has been analyzed and applied in 45 nm SOI CMOS for large RF power transistor cells. Moreover, various topologies of slow wave coplanar waveguide (CPW) lines are analyzed and implemented on the SOI substrate to synthesize inductors for matching networks at 60 GHz.

To demonstrate the active and passive design performance in 45nm SOI CMOS at 60 GHz, a two-stage cascode PA is presented. Measurement under continuous wave (CW) stimulus shows 18.2 dB gain, a 3 dB bandwidth of 20%, 14 dBm saturated output power at 22% peak power-added efficiency (PAE). Moreover, to validate the FET-stacking analysis, a three-stack PA is designed and fabricated with an output performance of 8.8 dB gain, a 3 dB bandwidth of 20%, 16 dBm saturated output power at 14% peak PAE. Finally, a wideband three stage amplifier is designed utilizing the two-stage cascode and three-stack PA, achieving 21.5 dB at gain over a fractional bandwidth of 20%, and 16 dBm saturated output power at 13.8% PAE.

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