Candidate
Maarten Aloys Jonkman
Title
Modified Differential Cascode Voltage Scale Logic Optimized for Sub-threshold Voltage Operation
Supervisor
Manoj Sachdev
Abstract
Ultra-low sub-threshold voltage research has become increasingly important with the shift in consumer electronics towards low power designs for mobile, wearable, and implantable technologies. These applications are able to trade-off speed for reduced power consumption and reduced minimum operating voltage. This thesis studies circuit design solutions that focus on achieving the lowest minimum operating voltages. These solutions will be most useful for applications where the supply voltage comes from energy harvesting sources that are only able to supply ultra-low voltages.
The logic circuit presented is a modified implementation of differential cascade voltage scale logic (DCVSL). Differential logic has improved ultra-low voltage performance over static CMOS logic and the modification to DCVSL offers a logic structure that can implement multi-input AND/NAND and OR/NOR gates while maintaining a stack height of one. The modification requires the use of capacitive boosting to allow for normal logic operation.