Wednesday, July 23, 2014 — 11:00 AM EDT

Candidate

Sriram Moorthy

Title

Characterizing Distortion in Successive-Approximation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit

Supervisor

David Nairn

Abstract

The Successive Approximation Analog-to-Digital converter (SAR-ADC) is a popular architecture due to its low power, simple design, and reasonable resolution and speed. Due to the prevalence of ADCs in modern hardware, it is important to investigate opportunities to reduce the cost of the circuit without performance losses. One measure of the ADC's performance is linearity. Linearity in the SAR-ADC is highly dependent on the linearity of its internal Digital-to-Analog converter (DAC). The DAC requires a reliable reference voltage in order output the correct result. A band-gap reference circuit is generally used in low power applications such as ADCs. However, the reference circuit's stability is limited by the internal DAC's fast transient load. Large off-chip bypass capacitors are used to maintain a stable reference voltage. Investigating how the bypass capacitor can be moved on-chip will help provide a solution for reducing space and costs of the ADC due to non-integrated components.

The off-chip capacitance within the reference circuit was varied to create a characteristic curve showing how distortion is affected. Once a relationship was determined through measurements, a Matlab model was generated to simulate the observed behaviour. Through simulation and circuit analysis, a relationship between the input voltage, off-chip capacitance and the voltage reference perturbations was found. With this insight, the process of designing a fully integrated solution without losses in linearity can begin.

Location 
EIT building
Room 3142

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