PhD Seminar: A DC to 43-GHz SPST with Minimum 50-dB Isolation and+19.6-dBm Large-Signal Power Handling in 45-nm SOI-CMOS

Candidate: Ayman Eltaliawy

Title: A DC to 43-GHz SPST with Minimum 50-dB Isolation and+19.6-dBm Large-Signal Power Handling in 45-nm SOI-CMOS

Date: November 26, 2020

Time: 2:30 PM

Place: REMOTE ATTENDANCE

Supervisor(s): Long, John

Abstract:

A fully-differential, single-pole single-throw (SPST) switch capable of high isolation in broadband CMOS transceivers is described. The SPST switch realizes > 50-dB isolation across DC to 43GHz while maintaining an insertion loss (IL) < 3dB. RF input power for -1dB compression (IP1dB) of the IL is +19.6dBm and the input third-order intercept point is +30.4dBm (both for differential inputs at 20GHz). The prototype is fabricated in 45-nm RF-SOI CMOS technology and has an active area of 0.0058mm2.