An Energy-Efficient System with Timing-Reliable Error-Detection Sequentials
Low power/energy digital design has become important, however, is faced with unavoidable obstacles such as process, voltage and temperature (PVT) variations. To overcome them, additional delay (slack) and/or voltage margins are typically required to ensure error-free operations even in the worst case. However, they restrict the clock frequency or consume extra energy. A new type of energy-efficient systems that integrate Error (timing errors or slack-deficit) Detection Sequential (EDS) circuits have been developed [6, 42, 25, 27]. In these systems, EDS-monitored paths convert the PVT variations into timing variations and the EDS circuits detect the induced errors (slack deficit or timing errors) and guide Dynamic Voltage Scaling (DVS) circuits to accordingly adjust the operating voltage to a proper lower level. Due to the quadratic relationship between energy and supply voltage, significant energy saving can be achieved. Nevertheless, the reliability of the EDS circuits acting as binary classifiers, the EDS-reliability, directly constrains the system reliability.
The EDS-reliability of EDS circuits can be evaluated by Mean Time Between Failure (MTBF) and viewed from two perspectives, the intrinsic and extrinsic EDS-reliability. The intrinsic EDS-reliability is caused by the metastability behavior of the synchronizers in EDS circuits which perform as a classifier in the timing domain (essentially synchronizer reliability). The MTBF of the synchronizers due to metastability and the synchronizer delay exclusively constrain each other and the metastability resolution timing constant ¬_ is the key coefficient to describe this constraining relationship. Though the number of synchronizers or EDS circuits in a system is usually only a few, their delays can occupy one or several clock cycles in pipeline designs and possibly constrain the system performance. Thus in synchronizer designs, the MTBF due to metastability is prioritized the highest and specified at the first place, while the synchronizer delay is usually weighted heavier than the energy consumption or area cost and targeted to be improved by methods such as reducing the _ of the synchronizer. The extrinsic EDS-reliability is defined as the avoidance of the actual timing errors when the EDS circuits are deployed to detect the errors (slack deficit or timing errors). This includes two perspectives, the speculative requirement that no direct timing errors should be generated when the EDS are detecting the errors and the accuracy requirement that the EDS circuits should detect the PVT variations accurately to avoid indirect timing errors. The extrinsic EDS-reliability depends on the EDS circuits deployment in the application systems.
EDS circuits (including synchronizers) have previously been designed and deployed in ASIC technologies operated at super-threshold supply voltages, however, do not work effectively under single low-voltage environments or for some applications such as FPGA-based Digital Signal Processing (DSP) circuits. Hence, this dissertation proposes a comprehensive analysis and new methodologies for the design and deployments of reliable EDS circuits in those circumstances.
Voltage-Boosted Synchronizers (VBSs) are proposed to improve the synchronizer performance with a specification of MTBF due to metastability under single low-voltage sup- ply environments. A VBS consists of a basic minimum-sized Jamb latch and a switched- capacitor-based charge pump. The capacitor of the charge pump is sized 14 times the area of the Jamb latch and provides a temporary voltage boost to the Jamb Latch to re- duce the _ and improves the metastability resolution time. Two powering strategies of the charge pump, namely Metastability-driven VBS (MVBS) and Clock-driven VBS (CVBS), are proposed. A new methodology for extracting the metastability parameters (such as _) of synchronizers under changing biasing currents is proposed. For a 1-year MTBF specification, MVBS and CVBS show 2.0-2.7 and 5.1-9.8 times the performance improvement over the basic Jamb latch, respectively, without incurring large power consumption.
VBSs are further modified and optimized to further improve the synchronizer performance. Process, Voltage and Temperature variations have great impact on synchronizer performance and it is difficult to post-silicon-calibrate synchronizers, thus a worst-case static analysis is necessary for synchronizer design. The capacitor of the charge pump is sized 130 times the area of the minimum MOS. Transistor-level optimization techniques including transistor sizing and forward body biasing are applied to the baseline and proposed synchronizers. A dynamic metastablity detector is proposed to reduce the feedback time of metastability detector and improve the overall synchronizer performance. For a common MTBF specification at typical (worst-case) PVT conditions, MVBS and CVBS show 2.4- 7.4 (4-95) and 4.8-11.1 (42-188) times the performance improvement over the basic Jamb latch, respectively, without incurring large power consumption.
To enhance the extrinsic EDS-reliability, a new EDS deployment methodology have been developed. The EDS circuits are augmented to the non-critical paths with high activations to assure the sampling accuracy and the duty cycle of the clock signal is tuned to achieve the speculative requirement. This methodology requires neither buffer insertion nor dual clocks and is applicable for FPGA implementations. An FPGA-based Discrete Cosine Transform with EDS and DVS circuits deployed in this fashion and demonstrates up to 16.5% energy saving over a conventional design at equivalent frequency setting and images quality, with a 0.3% logic element and 3.5% maximum frequency penalties.