BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Drupal iCal API//EN
X-WR-CALNAME:Events items teaser
X-WR-TIMEZONE:America/Toronto
BEGIN:VTIMEZONE
TZID:America/Toronto
X-LIC-LOCATION:America/Toronto
BEGIN:DAYLIGHT
TZNAME:EDT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZNAME:EST
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
DTSTART:20231105T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
UID:69e467ff49275
DTSTART;TZID=America/Toronto:20240422T143000
SEQUENCE:0
TRANSP:TRANSPARENT
DTEND;TZID=America/Toronto:20240422T153000
URL:https://uwaterloo.ca/institute-for-quantum-computing/events/deep-reinfo
 rcement-learning-perform-error-rate-aware-qubit
LOCATION:QNC - Quantum Nano Centre 200 University Avenue West 1201 Waterloo
  ON N2L 3G1 Canada
SUMMARY:Deep Reinforcement Learning to Perform Error Rate Aware Qubit Routi
 ng\nand Circuit Optimization
CLASS:PUBLIC
DESCRIPTION:IQC SEMINAR - ALEXANDER GEORGE-KENNEDY\, GEORGIA TECH\n\nQuantu
 m-Nano Centre\, 200 University Ave West\, Room QNC 1201 Waterloo\,\nON CA 
 N2L 3G1\n\nProtecting quantum information against noise is a widespread go
 al in\nquantum computation. In addition to implementing quantum error\ncor
 recting codes\, classical pre-processing steps of circuit\noptimization an
 d qubit routing can greatly increase the fidelity of\nthe result of a quan
 tum computation. Prior work has shown that neural\nnetworks and/or reinfor
 cement learning can be used to discover quantum\nerror correcting codes\, 
 perform qubit routing optimized for circuit\ndepth\, and find optimal poin
 ts to insert dynamical decoupling pulse\nsequences in a quantum circuit. W
 e extend prior work by creating a\ndeep reinforcement learning directed tr
 anspiler. We treat the problem\nof qubit routing and circuit optimization 
 together\, and can regard it\nas a single-player “game\,” where the ob
 jective is minimizing the\noutput circuit's estimated noise\, subject to t
 he connectivity\nconstraints of the architecture. The “moves” in this 
 game\navailable to the transpiler are selecting the qubit layout\,\nintrod
 ucing SWAP gates subject to architecture constraints\, and\nrewriting the 
 circuit according to equivalency rules (such as\nintroducing dynamical dec
 oupling sequences\, or simply optimizing away\nrepeated self-adjoint gates
 ). We train a transpiler for a specific\nquantum device\, in our experimen
 ts\, each of the available 5-qubit IBM\ndevices\, crucially including the 
 reported error rates per gate per\nqubit per device as part of the transpi
 ler training data. Running the\ntranspilers on a series of random circuits
  across different devices\,\nwe compare the transpiler output circuits wit
 h IBM's transpiler\noutputs. We find an average improvement of 17% reducti
 on in output\nerror rate compared to the IBM transpiler. This is an improv
 ement on\nprior work that also uses a neural network as a noise-indicating
 \nobjective function\, but with no explicit loading of device error\nrates
 \, a different vectorization of circuits\, and a greedy circuit\nrewrite p
 olicy. Our work is ongoing\, as we intend to extend the\ntranspiler's capa
 bility in the vein of prior work to construct error\ncorrecting codes duri
 ng optimization.
DTSTAMP:20260419T052831Z
END:VEVENT
END:VCALENDAR