Scaling up superconducting quantum computers

Thursday, May 31, 2018 2:30 pm - 2:30 pm EDT (GMT -04:00)

David P. Pappas, National Institute of Standards and Technology (NIST)

A brief history and overview of the requirements to guide the research and development for high-coherence superconducting quantum circuits will be given. The main focus will be on materials development at NIST. Topics will include identifying and mitigating loss due to amorphous two-level systems at interfaces and how to scale the fabrication of small aluminum-oxide tunnel junctions. The junctions were studied with atom probe microscopy to get an understanding of where the oxidation occurs. Fabrication of high-coherence circuits is demonstrated and the implementation of multi-pin packing to enable large-scale, 17-qubit chips is shown. Development of a new class of electro-plateable superconductor will be show that is being integrated with the packaging for a complete quantum circuit solution.