@conference {18166,
	title = {DynaSprint: Microarchitectural Sprints with Dynamic Utility and Thermal Management},
	booktitle = {In Proceedings of the 52nd IEEE/ACM International Symposium on Microarchitecture},
	year = {2019},
	pages = {426-439},
	address = {52nd Annual IEEE/ACM International Symposium on Microarchitecture, Columbus, OH},
	abstract = {Sprinting is a class of mechanisms that provides a short but significant performance boost while temporarily exceeding the thermal design point. We propose DynaSprint, a software runtime that manages sprints by dynamically predicting utility and modeling thermal headroom. Moreover, we propose a new sprint mechanism for caches, increasing capacity briefly for enhanced performance. For a system that extends last-level cache capacity from 2MB to 4MB per core and can absorb 10J of heat, DynaSprint-guided cache sprints improve performance by 17\% on average and by up to 40\% over a non-sprinting system. These performance outcomes, within 95\% of an oracular policy, are possible because DynaSprint accurately predicts phase behavior and sprint utility.},
	url = {https://dl.acm.org/citation.cfm?id=3358301},
	author = {Ziqiang Huang and Jose A. Joao and Alejandro Rico and Andrew D. Hilton and Benjamin C. Lee}
}
