<style face="normal" font="default" size="100%">Exploring the Impact of Switch Arity on Butterfly Fat Tree FPGA NoCs</style>

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<style face="normal" font="default" size="100%">Exploring the Impact of Switch Arity on Butterfly Fat Tree FPGA NoCs</style>

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<style face="normal" font="default" size="100%">Defer buffer</style>

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<style face="normal" font="default" size="100%">DynaSprint: Microarchitectural Sprints with Dynamic Utility and Thermal Management</style>

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<style face="normal" font="default" size="100%">Hardware Thread Scheduling</style>

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<style face="normal" font="default" size="100%">Decoupling Loads for Nano-Instruction Set Computers</style>