<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>25</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Jose Alberto Joao</style></author><author><style face="normal" font="default" size="100%">Alejandro Rico Carro</style></author><author><style face="normal" font="default" size="100%">Ziqiang Huang</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Hardware Thread Scheduling</style></title></titles><dates><year><style  face="normal" font="default" size="100%">2019</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://patents.google.com/patent/US10261835B2/en</style></url></web-urls></urls><edition><style face="normal" font="default" size="100%">United States of America</style></edition><volume><style face="normal" font="default" size="100%">10261835</style></volume><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">An apparatus has processing circuitry to execute instructions from multiple threads and hardware registers to store context data for the multiple threads concurrently. At a given time a certain number of software-scheduled threads may be scheduled for execution by software executed by the processing circuitry. Hardware thread scheduling circuitry is provided to select one or more active threads to be executed from among the software-scheduled threads. The hardware thread scheduling circuitry adjusts the number of active threads in dependence on at least one performance metric indicating performance of the threads.</style></abstract><issue><style face="normal" font="default" size="100%">U.S Patent and Trademark Office</style></issue><section><style face="normal" font="default" size="100%">US</style></section></record></records></xml>