<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>25</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Jose Alberto Joao</style></author><author><style face="normal" font="default" size="100%">Ziqiang Huang</style></author><author><style face="normal" font="default" size="100%">Alejandro Rico Carro</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Defer buffer</style></title></titles><dates><year><style  face="normal" font="default" size="100%">2019</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://patents.google.com/patent/US10275250B2/en</style></url></web-urls></urls><edition><style face="normal" font="default" size="100%">United States of America</style></edition><volume><style face="normal" font="default" size="100%">10275250</style></volume><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">An apparatus comprises processing circuitry for executing instructions of two or more threads of processing, hardware registers to store context data for the two or more threads concurrently, and commit circuitry to commit results of executed instructions of the threads, where for each thread the commit circuitry commits the instructions of that thread in program order. At least one defer buffer is provided to buffer at least one blocked instruction for which execution by the processing circuitry is complete but execution of an earlier instruction of the same thread in the program order is incomplete. This can help to resolve inter-thread blocking and hence improve performance.</style></abstract><issue><style face="normal" font="default" size="100%">U.S Patent and Trademark Office</style></issue><section><style face="normal" font="default" size="100%">US</style></section></record></records></xml>