Cisco Error Code Correction Analysis

Cisco Systems Canada is a large multinational corporation, which provides equipment, software, and support services that manage network traffic including data, voice, and video for a wide range of customers. The Silicon Engineering (SiE) team at Cisco Ottawa development centre design application-specific integrated circuit (ASIC) and other complex systems-on-a-chip (SoCs). As the ASICs and SoCs are so complex system, the development of the chip is broken into modules and assigned to smaller design teams. One of these block modules is the error code correction (ECC) element, which will be implemented as a sub-block in every memory to improve the reliability of the design. In 2013, the SiE team assigned to design a new ASIC routing processor and traffic manager that would be implemented in the next generation of Cisco routers. As a part of the design process, the team required to develop an efficient error correction code to ensure the reliability of the chip, minimize the resources used by ECC module, minimize power consumption and reduce delay. Generally, the SiE team uses single error correction/double error detection (SECDED) code method, Figure 1 [1].

Elsabé Coetzer, 4^th year Electrical Engineering student from University of Waterloo, was asked to analyze, evaluate, and compare two possible single error correction/double error detection (SECDED) code solution alternatives to be used by SiE Canada team.