|Title||Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs|
|Publication Type||Conference Paper|
|Year of Publication||2012|
|Authors||Kashif, H., H. D. Patel, and S. Fischmeister|
|Conference Name||Proceedings of the Asia South Pacific Design Automation Conference (ASPDAC)|
|Conference Location||Sydney, Australia|
|Keywords||NOC, shortest path algorithm|
We present a path selection algorithm that is used when deploying hard real-time traffic flows onto a chip- multiprocessor system. This chip-multiprocessor system uses a priority-based real-time network-on-chip interconnect between the multiple processors. The problem we address is the following: given a mapping of the tasks onto a chip-multiprocessor system, we need to determine the paths that the traffic flows take such that the flows meet there deadlines. Furthermore, we must ensure that the deadline is met even in the presence of direct and indirect interference from other flows sharing network links on the path. To achieve this, our algorithm utilizes a link-level analysis to determine the impact of a link being used by a flow, and its affect on other flows sharing the link. Our experimental results show that we can improve schedulability by about 8% and 15% over Minimum Interference Routing and Widest Shortest Path algorithms, respectively.