Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs

TitleUsing Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs
Publication TypeConference Paper
Year of Publication2012
AuthorsKashif, H., H. D. Patel, and S. Fischmeister
Conference NameProceedings of the Asia South Pacific Design Automation Conference (ASPDAC)
Date PublishedFebruary
Conference LocationSydney, Australia
ISBN Number2153-6961
KeywordsNOC, shortest path algorithm

We present a path selection algorithm that is used when deploying hard real-time traffic flows onto a chip- multiprocessor system. This chip-multiprocessor system uses a priority-based real-time network-on-chip interconnect between the multiple processors. The problem we address is the following: given a mapping of the tasks onto a chip-multiprocessor system, we need to determine the paths that the traffic flows take such that the flows meet there deadlines. Furthermore, we must ensure that the deadline is met even in the presence of direct and indirect interference from other flows sharing network links on the path. To achieve this, our algorithm utilizes a link-level analysis to determine the impact of a link being used by a flow, and its affect on other flows sharing the link. Our experimental results show that we can improve schedulability by about 8% and 15% over Minimum Interference Routing and Widest Shortest Path algorithms, respectively.

Refereed DesignationRefereed
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