Quantum computing (QC) has come a long way in device, architecture and algorithm domains. Recent advancement in fault-tolerant QC with technologies such as surface code, together with the technological progress in physical demonstration of silicon-based high-fidelity multiple quantum bits (qubits) has been a big step towards the dream of a complex quantum computer with potentially millions of qubits. The integration and/or interaction between classical CMOS and QC platforms is an emerging field of excitement.
Such application requires, at least in the near future, to operate CMOS at cryogenic temperatures (as low as millie Kevin) far below the conventional range of operating temperature (usually above -40C or -55C). In this direction, compact models for cryo-CMOS will be developed and calibrated deep sub-micron CMOS models at such temperature with electrical, thermal and noise behaviors. Scalable fault-tolerant QC architectures will be thoroughly considered to implement the error correction codes with a large number of qubits. Separate layers with CMOS modules, for functions such as controlling qubit operations, data readout and communication, will be designed and integrated in a compact and scalable way, to accommodate large numbers of qubits as well as stringent thermal budget.