Publications

Highly Qualified Personnel (HQP) under my direct supervisions are marked with *

Referred Journal Publications

  1. S. Wang, C. Xu, M. C. Tam, K. Vaillancourt, Z. Wasilewski, L. Wei, and D. Ban, "Visualization of localized facet Joule heating induced optical degradation on mid-infrared quantum cascade lasers," Opt. Express 30, 43342-43353 (2022)
  2. T. Guo, K. Pan*, Y. Jiao*, B. Sun, C. Du, J. P. Mills, Z. Chen, X. Zhao, L. Wei, Y. N. Zhou, and Y. Wul. "Versatile memristor for memory and neuromorphic computing." Nanoscale Horizons 7, no. 3 (2022): 299-310.
  3. Z. Yang*, K. Pan*, N. Zhou, and L. Wei, “Scalable 2T2R Logic Computation Structure: Design from Digital Logic Circuits to 3-D Stacked Memory Arrays,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 8, no. 2, pp. 84-92, Dec. 2022.
  4. H. H. Yang, M. Robitaille, X. Chen*, H. Elgabra*, L. Wei and N. Y. Kim, "Random Telegraph Noise of a 28-nm Cryogenic MOSFET in the Coulomb Blockade Regime," in IEEE Electron Device Letters, vol. 43, no. 1, pp. 5-8, Jan. 2022. (Yang, Robitaille and Chen have equal contributions.)
  5. B. Sun; S. Ranjan*, G. Zhou, T. Guo, C. Du, L. Wei, Y. N. Zhou, Y. Wu, “A True Random Number Generator Based on Ionic Liquid Modulated Memristors,” ACS Applied Electronic Materials, vol. 3, no. 5, pp 2380-2388, 2021.
  6. B. Sun, T. Guo, G. Zhou, S. Ranjan*, Y. Jiao, L. Wei, Y. N. Zhou, Y. A. Wu,“Synaptic devices based neuromorphic computing applications in artificial intelligence,” Materials Today Physics, vol. 18, No. 5, pp. 100393, 2021.
  7. T. Guo, B. Sun, S. Ranjan*, C. Du, B. J Kieffer, J. P. Mills, Y. Tong, L. Wei, Y. N. Zhou, Y. A. Wu, “Electrocatalytic Hydrolysis Modulated Multistate Resistive Switching Behaviors in Memristors,” Physica Status Solidi A: Applications and Materials Science, vol. 218, no. 8, pp. 2000655, 2021.
  8. B. Sun, S. Ranjan*, G. Zhou, T. Guo, Y. Xia, L. Wei, Y.N. Zhou, Y.A. Wu, “Multistate Resistive Switching Behaviors for Neuromorphic Computing in Memristor,” Materials Today Advances, vol. 9, pp 1-8, 2021.
  9. T. Guo, B. Sun, S. Ranjan*, Y. Jiao, L. Wei, Y. N. Zhou, Y. A. Wu, “From Memristive Materials to Neural Networks,” ACS Appl Mater Interfaces, vol. 12, no. 49, pp. 54243-54265, 2020.
  10. X. Chen*, S. Boumaiza, L. Wei, “Modeling Bias Dependence of Self-Heating in GaN HEMTs Using Two Heat Sources,” IEEE Transactions on Electron Devices, vol. 67, no. 8, pp. 3082-3087, 2020.
  11. S. Wang, C. Xu, F. Duan, B. Wen, S.M. S. Rassel, M. C. Tam, Z. Wasilewski, L. Wei, and D. Ban, “Thermal dynamic imaging of mid-infrared quantum cascade lasers with high temporal–spatial resolution,” Journal of Applied Physics 0128, 083106 (2020).
  12. S. Ranjan*, B. Sun, G. Zhou, Y. A. Wu, L. Wei, and Y. N. Zhou, “Passive Filters for Nonvolatile Storage Based on Capacitive-Coupled Memristive Effects in Nanolayered Organic–Inorganic Heterojunction Devices,” ACS Applied Nano Materials, vol. 3, no. 6, pp. 5045–5052, 2020.
  13. F. Duan, K. Chen, S. Wang, L. Wei, Y. Yu, D. Ban, “Temperature Profile and Transient Response of Thermally Tunable Ridge Waveguides with Laterally Supported Suspension,” Appl. Phys. Lett., vol. 116, pp. 011102, 2020.
  14. X. Chen*, S. Boumaiza, L. Wei, “Self-Heating and Equivalent Channel Temperature in Short Gate Length GaN HEMTs,” IEEE Transactions on Electron Devices, vol. 66, no. 9, pp. 3748-3755, 2019.
  15. Z. Yang*, S. Zarabi*, E. Fernandes*, I. Rua, H. Debeda, A. Salehian, D. Nairn, L. Wei, “A Simple Wireless Sensor Node System for Electricity Monitoring Applications: Design, Integration, and Testing with Different Piezoelectric Energy Harvesters,” Sensors, vol. 18, no. 11, pp. 3733, 2018.
  16. E. Fernandes*, M. Blake, I. Rue, S. Zarabi*, H. Debeda, D. Nairn, L. Wei, A. Salehian, “Design, Fabrication, and Testing of a Low Frequency MEMS Piezoelectromagnetic Energy Harvester,” Smart Materials and Structures, vol. 27, no. 3, pp.1-16, 2018.
  17. A. Tosson*, S. Yu, M. Anis, L. Wei, “Proposing a Solution for Single-Event Upset in 1T1R RRAM Memory Arrays,” IEEE Transaction on Nuclear Science, vol. 65, no. 6, pp. 1239-1247, 2018.
  18. A. Tosson*, S. Yu, M. Anis, L. Wei, “A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-based Neuromorphic Systems,” IEEE Transactions on Very Large Scale Integration, vol. 25, no. 11, pp. 3125-3137, 2017.
  19. H. Zhang*, M. Gupta, J. Watt, L. Wei, “Effective Drive Current for Pass-Gate Transistors,” IEEE Transactions on Electron Devices, vol. 63, no. 8, pp. 2999-3004, 2016.
  20. K. Sheikh*, S-J. Han, Lan Wei, “CNFET with Process Imperfection: Impact on Circuit-Level Yield and Device Optimization,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 12, pp. 2209-2221, 2016.

Referred Conference Publications

  1. R. Fang*, Y. Feng*, J. Chong*, K. Chan, U. Radhakrishna, L. Wei, “Comprehensive MVSG Compact Model for Power GaN Devices,” accepted by 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2023.
  2. R. Absar*, Z.D. Merino, H. Elgabra*, X. Chen, J. Baugh, L Wei, “Scalable Addressing Circuits for a Surface Code Quantum Computer in Silicon,” 2022 IEEE/ACM International Symposium on Nanoscale Architectures, Dec 2022.
  3. Y. Zhao*­, Y. Yoon, L. Wei, “A Multi-Level Simulation of GeH FETs: From Nanomaterial and Device Characteristics to Circuit Performance Optimization,” 2022 IEEE/ACM International Symposium on Nanoscale Architectures, Dec 2022.
  4. R. Fang*, D. Ma*, U. Radhakrishna, and L. Wei, “MVSG GaN-HEMT Model: Approach to Simulate Fringing Field Capacitances, Gate Current De-biasing, and Charge Trapping Effects,” 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, Phoenix, USA, Oct 2022 (Best Student Paper Award)
  5. P. Choi, R. Fang*, L. Wei, S. Boumaiza, U. Radhakrishna, and E. Fitzgerald, “Design of 20-28 GHz GaAs Phase Shifter MMIC and Small Signal Validation using MVSGaAs Model,” 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, Phoenix, USA, Oct 2022
  6. R. Absar*, Z.D. Merino, H. Elgabra*, X. Chen, J. Baugh, L Wei, “Scalable Addressing Circuits for a Surface Code Quantum Computer in Silicon,” 2022 Silicon Quantum Electronics Workshop, Orford, Quebec, Canada, Oct 2022.
  7. H. Elgabra*, F. Sfigakis, R. Absar*, X. Chen, J. Baugh, L Wei, “Cryogenic Virtual Source I-V Model for MOSFET Devices,” 2022 Silicon Quantum Electronics Workshop, Orford, Quebec, Canada, Oct 2022.
  8. K. Pan*, A. Tosson, N. Wang*, N. Y. Zhou and L. Wei, “A Novel RRAM and CR-based TCAM Design for High-speed and Energy-efficient Applications,”  IEEE/ACM Great Lakes Symposium on VLSI, May 2022.
  9. A. Q. Zhang*, A. M. S. Tosson and L. Wei, "Error Resilience and Recovery of Process Induced Stuck-at Faults in MLP Neural Networks using Emerging Technology," 2021 IEEE/ACM International Symposium on Nanoscale Architectures,  Nov 2021.
  10. K. Pan*, A. M. S. Tosson, N. Y. Zhou and L. Wei, "A Novel Programmable Variation-Tolerant RRAM-based Delay Element Circuit," 2021 IEEE/ACM International Symposium on Nanoscale Architectures, Nov 2021.
  11. X. Chen*, H. Elgabra*, C.-H. Chen, J. Baugh, L. Wei, “Estimation of MOSFET Channel Noise and Noise Performance of CMOS LNAs at Cryogenic Temperatures,” IEEE International Symposium on Circuits and Systems, pp. 1-5, Daegu, Korea, May 2021.
  12. Y. Zhao*, Y. Yoon, L. Wei, “A Multi-Level Simulation Scheme for 2D Material-Based Nanoelectronics,” IEEE International Conference on Nanotechnology, pp. 388-392, Montreal, Canada, Jul. 2020.
  13. K. Sheikh*, Lan Wei, “Reducing Impact of CNFET Process Imperfections on Shape of Activation Function by Using Connection Pruning and Approximate Neuron Circuit,” International Symposium on Quality Electronic Design, pp. 279- 284, Santa Clara, USA, Mar. 2020.
  14. S. Wang, C. Xu, F. Duan, B. Wen, SM S. Rassel, Z. Wasilewski, L. Wei, D. Ban, “Time-resolved Thermoreflectance Imaging for Mid-infrared Quantum Cascade Laser,” Conference on Lasers and Electro-Optics: Applications and Technology, Washington, DC United States, 10–15 May 2020
  15. Z. Yang*, Y. Ma*, L. Wei, “Functionally Complete Boolean Logic and Adder Design Based on 2T2R RRAMs for Post-CMOS In-Memory Computing,” IEEE/ACM Great Lakes Symposium on VLSI, pp 147-152, Washington, DC, USA, May 2019.
  16. Z. Yang*, L. Wei, “Logic Circuit and Memory Design for In-Memory Computing Applications Using Bipolar RRAMs,” IEEE International Symposium on Circuits and Systems, pp 1-5, Sapporo, Japan, May 2019.
  17. H. Elgabra*, B. Buonacorsi, C. Chen, J. Watt, J. Baugh, L. Wei, “Virtual Source based I-V Model for Cryogenic CMOS Devices,” International Symposium on VLSI Technology, Systems and Applications, pp. 1-2, Hsinchu, Taiwan, Apr. 2019.
  18. K. Sheikh*, L. Wei, “Methodology to Generate Approximate Circuits to Reduce Process Induced Degradation in CNFET Based Circuits,” International Conference on Simulation of Semiconductor Processes and Devices, pp. 360-363, Austin, USA, 2018.
  19. Z. Yang*, S. Zarabi*, E. Fernandes*, I. Rua, H. Debeda, A. Salehian, D. Nairn, L. Wei, “Electricity Monitoring System with Interchangeable Piezoelectric Energy Harvesters and Dynamic Power Management Circuitry,” IEEE International Conference on Nanotechnology, pp. 1-4, Cork, Ireland, Jul. 2018.
  20. K. Sheikh*, L. Wei, “Methodology to Capture Statistical Effect of Process Imperfections on Glitch Suppression in CNFET circuits and Counter Using Approximate Circuits,” IEEE/ACM Great Lakes Symposium on VLSI, pp. 27-32, Chicago, USA, May 2018.
  21. K. Sheikh*, L. Wei, “Evaluation of Circuit Performance Degradation due to CNT Process Imperfection,” International Symposium on VLSI Technology, Systems and Applications, pp. 1-2, Hsinchu, Taiwan, Apr. 2018.
  22. K. Sheikh*, L. Wei, “Using Approximate Circuits to Counter Process Imperfections in CNFET Based Circuits,” International Symposium on VLSI Design, Automation and Test, pp. 1-4, Hsinchu, Taiwan, Apr. 2018.
  23. H. Zhang*, A. Raslan, S. Boumaiza, L. Wei, “Physics based Compact Model of GaN HEMT with an Efficient Parameter Extraction Flow,” IEEE International Conference on ASIC, pp. 822-825, Guiyang, China, 2017.
  24. S. Zarabi*, E. Fernandes*, I. Rua, H. Debeda, C. Lucat, A. Salehian, D. Narin, L. Wei, “Design and Development of a Self-contained Integrated System for Electricity Monitoring Applications,” IEEE International Conference on ASIC, pp. 1125-1128, Guiyang, China, 2017.
  25. H. Debéda, I. Rua, E. Fernandes*, S. Zarabi*, D. Nairn, L. Wei, A. Salehian, “Printed MEMS-based Self-contained Piezoelectric-based Monitoring Device for Smart Grids,” International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Application, Journal of Physics: Conference Series,vol. 1052, pp. 012111, Kanasawa, Japan, Nov. 2017.
  26. I. Rua, H. Debéda, E. Fernandes*, S. Zarabi*, D. Nairn, L. Wei, A. Salehian, “Optimization of the Fabrication of a Low Frequency Energy Harvester Made of Printed PZT Layers on a Meander Shape Stainless Substrate,” Conference on Design, Test, Integration and Packaging for MEMS/MOEMS, pp. 62-67, Bordeaux, France, May 2017.
  27. A. Tosson*, S. Yu, M. Anis, L. Wei, “Impact of the RRAM Reliability Failures on the Performance of the RRAM-based Neuromorphic Systems,” IEEE Computer Society Annual Symposium on VLSI, Bochum, Germany, Jul. 2017.
  28. A.Tosson*, S. Yu, M. Anis, L. Wei, “Mitigating the Effect of the Reliability Soft-errors of the RRAM Devices on the Performance of the RRAM-based Neuromorphic Systems,” IEEE/ACM Great Lakes Symposium on VLSI, pp. 53-58, Banff, Canada, May 2017.
  29. E. Fernandes*, S. Zarabi*, H. Debéda, C. Lucat, D. Nairn, L. Wei, A. Salehian, “Modelling and Fabrication of a Compliant Centrally Supported Meandering Piezoelectric Energy Harvester Using Screen-printing Technology,” International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Application, Journal of Physics: Conference Series , vol. 773, pp. 012109, Paris, France, Nov. 2016.
  30. A.Tosson*, M. Anis, L. Wei, “RRAM Refresh Circuit: A Proposed Solution to Resolve the Soft-Error Failures for HfO2/Hf 1T1R RRAM Memory Cell,” IEEE/ACM Great Lakes Symposium on VLSI, pp. 227-232, Boston, USA, May 2016.
  31. A. Tosson*, A. Neale, M. Anis, L. Wei, “8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design,” IEEE/ACM Great Lakes Symposium on VLSI, pp. 239-244, Boston, USA, May 2016.

Seminar and invited talks

  1. R. Absar*, H. Elgabra*, X. Chen, F. Sfigakis, J. Baugh and L. Wei, “Scalable Addressing Circuits for a Surface Code Quantum Computer in Silicon,” IEEE Electron Devices Technology and Manufacturing (EDTM) Conference, 2023.
  2. Lan Wei, “Recent Progress in MVSG_CMC GaN HEMT Compact Model,” The 8th International Forum on Wide Bandgap Semiconductors, 2023.
  3. Long Ma, Lan Wei, “Accurate and Efficient Modeling of the Trapping Effects in GaN HEMTs,” PathWave Design 2023 Webinar Series, Keysight Technologies, 2022.
  4. X. Chen*, S. Boumaiza, L. Wei, “Self-heating in Short-channel GaN HEMTs: Maximum Channel Temperature and Equivalent Channel Temperature, IEEE Electron Devices Technology and Manufacturing (EDTM) Conference, 2022.
  5. J. Baugh, R. Absar*, H. Elgabra*, X. Chen*, F. Sfigakis, L. Wei, “Challenges for Building a Silicon-based Quantum Computer,” International Symposium on Quality Electronic Design, 2021.
  6. L. Wei, “Introduction to Quantum Computing,” Forum on Electronics for a Quantum World, International Solid-State Circuits Conference, 2021.
  7. K. A. Abrar, L. Wei, U. Radhakrishna, “Modeling Layout, Distribution and Breakdown Effects in GaN HEMTs in the MVSG Approach,” IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2019. 
  8. A. Tosson*, S. Yu, M. Anis, L. Wei, “1T2R: A Novel Memory Cell Design to Resolve Single-Event Upset in RRAM Arrays,” IEEE International Conference on ASIC, pp. 918, 2017.
  9. X. Chen*, U. Radhakrishna, L. Wei, “MVSG Model for RF Applications: Thermal, Scalability and Parasitic Modeling,” International MOS-AK Workshop, Silicon Valley, USA, 2019. 
  10. L. Wei, K. Sheikh*, “Using Approximate Circuit to Improve Process Induced Failure in CNFET Circuits,” Carbon Nanotube Thin Film Electronics and Applications Symposium, 2018.
  11. K. Sheikh*, S-J.Han, L. Wei, “Impact of CNT Process Imperfection on Circuit-level Functionality and Yield,” IEEE International Symposium on Circuits and Systems, pp. 401-404, 2016. 
  12. L. Wei, “Technology Assessment Based on Device and Circuit Interaction and Optimization,” CMOS Emerging Technologies Research, Vancouver, Canada, 2015.