Worst-case execution bounds for real-time programsare profoundly impacted by the latency of accessing hardwareshared resources, such as off-chip DRAM. While many differentmemory controller designs have been proposed in the literature,there is a trade-off between average-case performance and pre-dictable worst-case bounds, as techniques targeted at improvingthe former can harm the latter and vice-versa. We find thattaking advantage of pipelining between different commands canimprove both, but incorporating pipelining effects in worst-caseanalysis is challenging. In this work, we introduce a novelDRAM controller that successfully balances performance andpredictability by employing a dynamic pipelining scheme. Weshow that the schedule of DRAM commands is akin to a two-stagetwo-mode pipeline, and hence, design an easily-implementableadmission rule that allows us to dynamically add requests to thepipeline without hurting worst-case bounds.