Lan Wei
About
Dr. Lan Wei is an associate professor and Tier 2 Canada Research Chair in the Department of Electrical and Computer Engineering at the University of Waterloo.
She received her B.S. in Microelectronics and Economics from Peking University, Beijing, China, in 2005 and her M.S. and Ph.D. in Electrical Engineering from Stanford University, Stanford, USA (with Professor H.–S. Philip Wong), in 2007 and 2010, respectively. Before joining the University of Waterloo in 2014, Dr. Wei worked at Altera Corporation in San Jose, California, where her responsibilities included foundary technology evaluation, power management and Stratix X FPGA product development with Intel 14nm technology. She also worked as a postdoctoral associate in Microsystems Technology Laboratories, Massachusetts Institute of Technology, under Professor Dimitri Antoniadis. Her research focuses on device-circuit interactive design and optimization, cryogenic CMOS electronics for quantum computing, error-resilient computation, and integrated electronic systems using emerging technologies including GaN, RRAM and low-dimensional materials.
Dr. Wei has served on the Technical Program Committee of several academic conferences, including IEDM (2011-2012, 2021-2022), DATE (2021-), ICCAD (2019-), VLSI-TSA (2013-), GLSVLSI (2017-), ISQED (2019-), ISLPED (2013), etc., and was listed as one of the key contributors to the Process Integration, Devices, and Structures Chapter (PIDS) of the International Technology Roadmap for Semiconductors (ITRS) 2009 Edition. She is the co-developer of the MIT Virtual Source GaN HEMT (MVSG) Compact Model, which is an industry standard approved and supported by the Compact Model Coalition for GaN HEMT compact model.