Worst-Case Latency Analysis for the Versal Network-on-Chip
Candidate: Ian Elmor Lang
Title: Worst-Case Latency Analysis for the Versal Network-on-Chip
Date: December 16, 2021
Time: 15:00
Place: online
Supervisor(s): Kapre, Nachiket - Pellizzoni, Rodolfo
Abstract:
The recent line of Versal FPGA devices from Xilinx Inc. includes a hard NetworkOn-Chip (NoC) embedded in the programmable logic,
designed to be a high-performance system-level interconnect. While the target markets for Versal devices include applications
