Lecture 1:
Rethinking Chip Design in the Age of AI
Speaker: Professor Mehdi Saligane, ECE Department, Brown University, Rhode Island
Date: April 30, 2026
Time: 1:00pm to 2:00pm
Location: EIT 3142
Abstract:
AI is changing not only the applications we build, but also the way we design the chips that power them. This talk explores how we can rethink chip design in the age of AI from two complementary directions: using AI to automate and improve chip design, and building specialized chips that make AI dramatically more efficient.
On the design side, we present Agentic-RL gLayout, a reinforcement-learning framework for analog layout generation that replaces manual heuristics with goal-driven planning and self-correction. Built on open-source tools such as OpenROAD, gLayout, and OpenFASOC, it enables cleaner, more compact, and rule-compliant layouts with far less manual effort. On the architecture side, we present a hardware-software co-design stack for efficient edge AI, reducing latency and energy in LLM inference. By co-optimizing models, precision, and accelerator design, this approach supports fast, privacy-preserving inference under tight power constraints. Taken together, these efforts illustrate a broader shift toward open, AI-enabled chip design flows and domain-specific AI hardware. The result is a faster, more automated, and more accessible path to silicon in the age of AI.
Biography:
Mehdi Saligane is an Assistant Professor of Electrical and Computer Engineering at Brown University. He is a founding member of the OpenROAD and OpenFASOC projects and has played a leading role in advancing open, accessible, and automated chip design. Before joining Brown in 2025, he was a Research Faculty member at the University of Michigan and joined Google Research as a Visiting Faculty Member in 2024.
Dr. Saligane has received the 2023 Google Cloud Research Innovators Award and the 2021 Google Research Faculty Award. He has also held several leadership roles in the open-source silicon community, including within CHIPS Alliance and the IEEE Solid-State Circuits Society (SSCS), where he currently chairs the Open-Source Ecosystem Technical Committee (TC-OSE). He co-founded and organizes the SSCS Chipathon Design Contest and the SSCS Code-a-Chip Notebook Competition, helping grow a global community around open-source chip design, education, and innovation.
Lecture 2:
Research and Open-Source EDA Tools
Speaker: Tim Edwards, Open Circuit Design
Date: April 30, 2026
Time: 2:00pm to 3:00pm
Location: EIT 3142
Abstract:
This presentation describes the IC design flow when performing research with open-source, non-academic EDA tools. The tools maintained and develop by Tim are used as examples (e.g., magic, netgen, capiche, open_pdks, and others), but he will discuss other commercial and organizational open-source tools, such as OpenROAD, LibreLane, and others. Tim’s talk is outlined below:
(1) History of open-source EDA tools
(2) Magic's cutting edge (at the time) DRC and parasitic extraction
(3) The Dark Ages of Open-Source EDA
(4) The first open PDK development: Efabless, Google, and SkyWater
(5) Circuit design and synthesis examples: MultiGiG to Raven to today
(6) Magic's extraction revisited: FasterCap and Capiche
(7) Hierarchical R-C extraction with analytical capacitor models
Biography:
Tim Edwards is an open-source silicon advocate and principal in the consulting/contracting company Open Circuit Design, which specializes in open-source EDA tool development and custom chip design. He is the developer and maintainer of multiple popular open-source software tools for EDA, including magic (custom layout), netgen (LVS), and open_pdks (PDK compiler). As Senior Vice-President of Analog at Efabless from 2014 to 2025, he was one of the principal developers of the sky130 and gf180MCU open PDKs, and has assisted in the development of IHP’s sg13g2 and sg13cmos5l open PDKs. Tim designed the Efabless "Raven" RISC-V SoC chip in 2018 using an all-open-source tool flow, architected the "Caravel" multi-project harness chip and its derivatives, and ran the "Chipalooza" analog circuit design challenge.