A University of Waterloo Electrical and Computer Engineering (ECE) research team has received the Stamatis Vassiliadis Award for Best Paper at the 36th International Conference on Field-Programmable Logic and Applications (FPL 2026), held in Ghent, Belgium.
The team includes Emir Guevara, an Electrical Engineering alumnus and current ECE PhD student; Gavin Lusby, a current Computer Engineering undergraduate student; Chaitanya Sharma, who graduated from Computer Engineering in 2026; and ECE professor, Dr. Nachiket Kapre.
Their award-winning paper, “Cocotb-PYNQ-PR: From Co-Simulation to Deployment: A Unified DFX Framework for PYNQ,” presents an open-source framework that allows FPGA partial-reconfiguration designs to be tested in simulation and then deployed on PYNQ hardware through a unified workflow.
Partial reconfiguration allows part of a field-programmable gate array (FPGA) to be replaced at runtime while the rest of the system continues operating. However, PYNQ previously had no native simulation support for testing this behaviour. Developers had to build and deploy their designs to a physical board simply to determine whether a module swap worked correctly, resulting in long waits between tests and limited visibility into problems.
“We wanted to make it possible to catch these problems before deployment and reduce the manual work needed to get a design running on hardware,” Guevara says.
Guevara compares an FPGA to a machine made of LEGO blocks. With partial reconfiguration, one section can be taken apart and rebuilt to perform a different function without stopping the entire machine. The challenge is ensuring that the rebuilt section continues to work with everything around it, including during the change.
“Our framework provides a computer simulation of that machine, so developers can try those changes and spot problems before committing to a hardware build,” Guevara says. “It then automates the work needed to put the design onto AMD FPGAs, using the same test in both the virtual and physical versions.”
AMD has demonstrated partial reconfiguration in applications including video analysis, encryption and signal processing. The team’s framework could help researchers and industry partners explore similar applications on supported AMD FPGA platforms through PYNQ, with less development effort and high-performance deployment. By simplifying design and testing while reducing the time required to switch hardware functions, the framework makes these systems easier to develop and more practical to use.
The framework currently supports boards based on AMD’s Zynq and Zynq UltraScale+ devices. The researchers hope to extend support to PYNQ-enabled RFSoC boards and collaborate with AMD to integrate the changes introduced in PYNQ 4.0.
Congratulations to Guevara, Lusby, Sharma and Kapre on this outstanding achievement. Their success highlights the exciting research opportunities available to students in the Department of Electrical and Computer Engineering, where they can work alongside leading researchers, contribute to emerging technologies and gain meaningful hands-on experience that extends far beyond the classroom.