ECE 730 Topic 16 - Spring 2018

ECE 730 Topic 16 - Embedded Semiconductor Memories

Instructor

Professor Manoj Sachdev

Calendar Description:
Static and dynamic behavior of MOS transistor short channel effects and scaling trends. Memory
architectures and building blocks. SRAM, DRAM, and CAM cell design and analysis. Low- power, low-voltage circuit techniques. Memory yield, redundancy and reliability issues.

Prerequisite: ECE 445 or equivalent course
*Project

Detailed description Lecture Hours

1. MOS Transistor & Inverter Review

  • Static behavior
  • Parasitic capacitances and dynamic behavior
  • Short channel effects
  • Scaling concept
6

2. Static Random Access Memory Circuits – I

  • Architecture and building blocks
  • SRAM cell designs and analysis
  • Peripheral circuits – address decoders, sense amplifiers, pre-charge & equalize
8

3. Static Random Access Memory Circuits – II 

  • Variability and SRAM circuits
  • Low-Voltage, Low-Power SRAMs
  • Parasitics and Timing Design
  • Robust circuit design
8

4.  Dynamic Random Access Memory & Content Addressable Memories

  • DRAM circuits – cells, sense amplifiers, Timing and control
  • CAM cell design
  • Peripheral circuits – matchline sensing, Priority encoder
6

5.  Memory Test and Reliability 

  • Defects in manufacturing
  • Memory fault models and test algorithms
  • Soft errors in memories
  • Redundancy, Repair and Yield
8
Total hours 36


References:

  1. Lecture Notes
  2. A. Pavlov, and M. Sachdev, CMOS SRAM – Circuit Design and Parametric Test in Nano-scaled Technologies, Springer, ISBN 978-1-4020-8362-4
  3. J. Rabaey et. al., “Digital Integrated Circuits: A Design Perspective, 2nd edition, Prentice Hall, 2003, ISBN 0-13-090996-3

Project:  An individual project is an essential component of this course.