FPGA Acceleration of Deep Learning Recommendation Models
Deep learning recommendation models (DLRMs) are a key workload for many service providers such as Alibaba, Amazon, Google, Meta, and Netflix. They are used to recommend products you might like on online retail websites, suggest shows to watch next on streaming services, or predict the click-through rates for online ads and news feeds. In this project, you will first learn about the DLRM computational workload and then design specialized hardware for accelerating it on one or multiple field-programmable gate arrays (FPGAs). Prior experience of digital hardware design, Verilog or SystemVerilog, and RTL simulation is necessary. Familiarity with FPGA architecture and CAD is a plus.
Supervisor: Prof. Andrew Boutros
Email: andrew.boutros@uwaterloo.ca
Hardware Architecture for Machine Learning Algorithms Based on Stochastic Computing
In this project, you will implement an RTL hardware architecture for a convolutional neural network (CNN) based on stochastic computing, which offers compact arithmetic node implementation, to be applied to problems in medical imaging. The target will be a field-programmable gate array (FPGA) platform.
Supervisor: Prof. Vincent Gaudet
Email: vcgaudet@uwaterloo.ca
Linux Perf Integration for Hardware Performance Counters on a RISC-V CVA6 Processor
Hardware performance counters (HPCs) expose low-level microarchitectural events — cache misses, branch mispredictions, pipeline stalls, and more; that are essential for application profiling and optimization. The RISC-V CVA6 processor defines a rich set of such counters, but Linux perf support for them remains limited, restricting developers from using standard profiling workflows on this platform. This project will implement full Linux perf support for the CVA6 HPCs by extending the RISC-V perf kernel driver, adding the necessary OpenSBI HPM extensions for privileged counter access, and mapping CVA6-specific hardware events to the perf event model. The student will validate the implementation by profiling real workloads on an FPGA-deployed CVA6 based multicore SoC and measuring monitoring overhead.
Required knowledge & skills: Linux kernel programming (C), computer architecture fundamentals, familiarity with the RISC-V privileged ISA. Prior exposure to embedded Linux development is appreciated but not required.
Supervisor: Prof. Rodolfo Pellizzoni
Email: rpellizz@uwaterloo.ca
Location: E5 4113
Modifying RISC-V based System on Chip to support memory tagging-based Quality of Service
The goal of this project is to modify our RISC-V based SoC platform to support memory tagging-based QoS, specifically the newly ratified CBQRI extension ( https://docs.riscv.org/reference/cbqri/v1.0/index.html ). The scope of this project includes (1) Implementing propagation of CBQRI bits from the core through the memory subsystem and (2, if time permits) the memory side controllers which take these bits and perform regulation/partitioning of memory resources.
Required Knowledge: Computer Architecture, RTL Design. Strong understanding of the RISC-V ISA and its various extensions is a plus.
Supervisor: Prof. Rodolfo Pellizzoni
Email: rpellizz@uwaterloo.ca
Location: E5 4113
Snapshot-Based Performance Counter Access for SoC Monitoring
Modern system-on-chip platforms rely on hardware performance counters to monitor system activity and support runtime resource management. In the CVA6-based platform used in this project, the Advanced Platform Monitoring Unit (APMU) provides a set of hardware counters that monitor system-level events such as cache misses, interconnect traffic, and memory requests. These counters are accessed by software running on an embedded Ibex core within the APMU. However, because counters continuously increment during execution, software reads may observe inconsistent values when multiple counters are accessed sequentially. This project aims to design a snapshot mechanism that allows software to capture a consistent view of all performance counters at a specific point in time. The solution will involve adding a shadow register structure that stores counter values when triggered by a special instruction or control signal from the embedded Ibex control core. The student will implement the snapshot logic in RTL and integrate it into the existing monitoring infrastructure.
Required knowledge & skills: digital logic design, RTL (Verilog/SystemVerilog), computer architecture fundamentals. Familiarity with RISC-V architecture is appreciated but not required.
Supervisor: Prof. Rodolfo Pellizzoni
Email: rpellizz@uwaterloo.ca
Location: E5 4113
Real-Time Control and Embedded Systems for Motion Fidelity Driving Simulators
This project aims to develop a high-fidelity driving simulator that prioritizes motion cues to maximize driver retention and recall in training scenarios. A six-degree-of-freedom motion platform with linear actuators will reproduce translational and rotational dynamics, driven by real-time vehicle physics. Embedded controllers will regulate actuator signals, ensuring accurate and synchronized motion feedback. The simulator scenarios will focus on developing the telemetry within hazardous, and intentionally high-risk driving conditions that cannot be safely practiced in traditional training, such as braking on ice, hydroplaning, and collision avoidance. The project will also design a data acquisition pipeline for logging vehicle dynamics, actuator states, and driver biometrics emphasizing communication interfaces, signal processing, and embedded control systems.
Supervisor: Prof. Oliver Schneider
Email: oliver.schneider@uwaterloo.ca
Phone: 519-888-4567 x38505
Location: CPH 3627
Supervisor: Prof. Siby Samuel
Email: siby.samuel@uwaterloo.ca
Phone: 519-888-4567 x37656
Location: EC4 2119