Publications
DynaSprint: Microarchitectural Sprints with Dynamic Utility and Thermal Management. In In Proceedings of the 52nd IEEE/ACM International Symposium on Microarchitecture (pp. 426-439). Retrieved from https://dl.acm.org/citation.cfm?id=3358301 micro2019-final503.pdf
. (2019). Decoupling Loads for Nano-Instruction Set Computers. In Proceedings of the 43rd International Symposium on Computer Architecture (Vol. 44, pp. 406-417). Retrieved from https://dl.acm.org/citation.cfm?id=3001181 p406-huang.pdf
. (2016). Defer buffer. US Patent No. 10275250. U.S Patent and Trademark Office. Retrieved from https://patents.google.com/patent/US10275250B2/en
. (2019). Hardware Thread Scheduling. US Patent No. 10261835. U.S Patent and Trademark Office. Retrieved from https://patents.google.com/patent/US10261835B2/en
. (2019). Exploring the Impact of Switch Arity on Butterfly Fat Tree FPGA NoCs. In The 28th IEEE International Symposium On Field-Programmable Custom Computing Machines. fccm20-camera-ready.pdf
. (2020).