|Title||A hardware implementation of real-time video deblocking using shifted thresholding|
|Publication Type||Conference Paper|
|Year of Publication||2007|
|Authors||Hansen, M., A. Wong, and W. Bishop|
|Conference Name||20th Canadian Conference on Electrical and Computer Engineering|
|Keywords||bit shifting operation, block codes, block-transform coding technique, computer architecture, data compression, digital arithmetic, digital video content transmission, division operation, field programmable gate array board, field programmable gate arrays, FPGA board, hardware architecture, hardware complexity, integer arithmetic operation, MPEG encoding, multimedia communication, real-time video deblocking algorithm, shifted thresholding algorithm, transform coding, video coding, video communication, video compression|
Video compression has become very important as demand has increased for the storage and transmission of digital video content. Popular video compression schemes like MPEG encoding make use of block-transform coding techniques which are susceptible to blocking artifacts. Recently, an efficient deblocking algorithm based on the concept of shifted thresholding has been proposed. This algorithm uses only integer arithmetic and replaces division operations with bit shifting. This paper proposes a new hardware architecture for the implementation of video deblocking using shifted thresholding. A prototype system for high performance video deblocking using a FPGA (field programmable gate array) board is described. The prototype system leverages the reduced hardware complexity of the shifted thresholding algorithm to cost-effectively implement video deblocking on a FPGA board.