IEEE Solid-State Circuits Society K-W Section Distinguished Lecture

Title: The Road to Gate-All-Around CMOS and its Impact on Analog Design

Speaker: Dr. Alvin Loke, Senior Principal Engineer, Intel Corporation

Date: March 25, 2025

Time: 1:30pm to 4:30pm

Location: E7 7303/7363

Abstract:

Despite the much debated end of Moore's Law, CMOS scaling still maintains economic primacy with 3-nm FinFET SoCs already in the marketplace for several years and 2-nm gate-all-around SoCs anticipated this year. Modest feature size reduction and design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled FinFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the stage for motivating the gate-all-around (GAA) transistor architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are fabricated. We will then shift to the challenges that CMOS scaling has imposed on analog design. To address the growing effort required for analog/mixed-signal design, we will cover design strategies on how analog design has adapted and thrived through decades of increasingly unfriendly scaling, including the migration to heterogeneous integration.

About Alvin Loke:

Dr. Alvin Loke is a Senior Principal Engineer at Intel Corporation, San Diego, working on analog design/technology co-optimization for Intel’s Angstrom-era CMOS nodes. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. He received a BASc in engineering physics from the University of British Columbia, and M.S. and Ph.D. degrees in electrical engineering from Stanford University. After several years in CMOS process integration, Dr. Loke has since worked on analog/mixed-signal design, focusing on a variety of wireline links, design/model/technology interface, and analog design methodologies.

Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as a Distinguished Lecturer, AdCom Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as an IEEE-CICC Technical Program Committee member, and JSSC, SSC-L, and Solid-State Circuits Magazine Guest Editor. He currently serves as the IEEE-VLSI Symposium Secretary, SSCS Global Chapters Chair, and as a Distinguished Lecturer. Dr. Loke has authored over 70 publications and delivered invited short courses at the ISSCC, VLSI Symposium, CICC, and BCICTS meetings. He holds 29 US patents.