Candidate
Adam Bray
Title
A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog to-Digital Converters
Supervisor
Nairn, David
Abstract
Time-interleaved analog-to-digital converters (TI-ADCs) are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and manufacturing variations, timing skews occur between the sampling clocks of the sub ADCs within the TI-ADC. These timing skews compromise the spurious free dynamic range (SFDR) of the converter. In addition, jitter on the sampling clocks, degrade the signal-to-noise ratio (SNR) of the TI-ADC. Therefore, in order to maintain an acceptable SFDR and SNR, it is necessary to correct the timing skews while adding minimal jitter.
Two analog-based architectures for correcting timing skews were investigated, with one being selected for implementation. The selected architecture and additional test circuitry were designed and fabricated in a 0.18µm CMOS process and tested using a 125 MSPS 16-bit ADC. The circuit achieves a correction precision on the order of 10's of femtoseconds for timing skews as large as approximately 180 picoseconds, while adding less than 200 femtoseconds of rms jitter.