Candidate: Jenny Yu
Title: Benchmarking and Optimizing AES for Lightweight Cryptography on ASICs
Date: December 19, 2019
Place: EIT 3151
Supervisor(s): Aagaard, Mark D.
There have been numerous works focused on optimizing the AES cipher to minimize area. Even with the notion of gate equivalents, the di erent tools and ASIC libraries used to synthesize the designs makes it hard to objectively compare them. We benchmark and analyze AES-128 encryption cores by implementing and synthesizing them using a set of four ASIC libraries. We show how di erent implementations of internal AES functions lend themselves better to di erent architectural options. Using this analysis, we design our own 8-bit AES encryption core, which has a 13% improvement in area and 9% improvement in throughput/area2 over the next smallest design on STMicro’s 65 nm process. It has an area of 1960 GE and a latency of 216 clock cycles.
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