Tuesday, August 6, 2013 — 2:00 PM EDT

Speaker

Conor O'Sullivan

Title

Test Chip Design for Process Variation Characterization in 3D Integrated Circuits

Abstract

A test chip design is presented for the characterization of process variations and Through Silicon Via (TSV) induced mechanical stress in 3D integrated circuits. The chip was designed, layed-out, and taped-out for fabrication in a 130nm Tezzaron/GlobalFoundries process through CMC Microsystems. The test chip takes advantage of the architecture of 3D ICs to improve its throughput of measured data. Its design splits the circuitry of its test structures to ensure that its measured devices are spaced with a high density that cannot be achieved on a 2D IC. The design also has a high spatial resolution and measurement fidelity compared to similar 2D variation characterization test structures.

The test chip was simulated to have an improved measurement accuracy compared to conventional variation characterization designs. Background leakage subtraction and radial filtering are two techniques that can be applied to the chip's measurements to reduce its error further for subthreshold device current measurements and stress-induced mobility measurements, respectively. Experimental measurements can be taken from the chip using a custom PCB measurement setup once the chip has returned from fabrication.

Supervisors

Professors Siddarth Garg and Peter Levine

Location 
E5 building
Room 4106/4128

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