MASc Seminar: An Implementation of a Predictable Cache-coherent Multi-core SystemExport this event to calendar

Thursday, April 25, 2019 — 1:00 PM EDT

Candidate: Paulos Tegegn

Title: An Implementation of a Predictable Cache-coherent Multi-core System

 

 

Date: April 25, 2019

Time: 1:00PM

Place: EIT 3151-3153

Supervisor(s): Patel, Hiren D.

 

Abstract:

Multi-core platforms have entered the realm of the embedded systems to meet the ever growing performance requirements of the real-time embedded applications. Real-time applications leverage the hardware parallelism from multi-cores while keeping the hardware cost minimum. However, when the real-time tasks are deployed on the multi-core platforms, they experience interference due to sharing of hardware resources such as shared bus, last level cache, and main memory. As a result, it complicates computing the worst-case execution time of the real-time tasks. In this thesis, I present a hardware prototype that implements a predictable cache-coherent real-time multi-core system. The designed hardware follows the design guidelines outlined in the predictable cache coherence protocol. The hardware uses a latency insensitive interfaces to integrate the multi-core components such as the processor, cache controller, and interconnecting bus. The prototyped multi-core hardware is synthesized and implemented in a low-cost and high-performing FPGA board. The hardware is validated and verified on a tethered system that enables the design to run multi-threaded pthread applications.

 

Location 
EIT
Room 3151-3153
200 University Avenue West

Kitchener, ON N2L 3G1
Canada

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