Wednesday, July 20, 2022 — 2:00 PM EDT

Candidate: Haien Ma
Title: A 39GHz Balanced Power Amplifier with Enhanced Linearity in 45nm SOI CMOS
Date: July 20, 2022
Time: 14:00
Place: online
Supervisor(s): Boumaiza, Slim

Abstract:

This thesis presents a balanced power amplifier design with enhanced linearity in Glob[1]alFoundries’ 45nm silicon-on-insulator

(SOI) CMOS technology. By using the balanced topology with each stage terminating with a differential 2-stacked architecture, the PA achieves saturated output power of over 21 dBm. Each of the two identical sub-PAs in the balanced topology uses 2-stage topology with driver and PA co-design method. The linear[1]ity is enhanced through careful choice of biasing point and a strategic inter-stage matching network design methodology, resulting in amplitude-to-phase distortion below 1 degree up to the output 1dB compression level of over 19 dBm. The balanced amplifier topology significantly reduces the PA performance variation over mismatched load impedance at the output, thus improving the PA performance over different antenna active impedance caused by varying phased array beam-steering angles. In addition to this, the balanced topology also optimizes the PA input and output return loss, giving matching better than -20 dB at both input and output and minimizing the risk of potential issues and performance degradation in the system integration phase. Lastly, the compact transformer based matching networks and quadrature hybrids reduce the chip area occupation of this PA, resulting in a compact design with competitive performance.

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