Name: Hoda Barkhordar-pour
Date: Dec 13, 2022
Time: 3:00pm
Location: Teams
Supervisors: Slim, Boumaiza, Patrick Mitran
Title: Realtime Hardware Implementation of Digital Predistortion Technique for MIMO Transmitters
Abstract: As one of the key enabling technologies of 5G networks, massive multiple-input, multiple-output (MIMO) transmitters utilize a large number of transmit chains to ensure a very high data rate and acceptable signal quality. Realizing Massive MIMO not only includes increasing antenna count but also, proportionally, requires a higher number of power amplifiers (PAs). Digital predistortion (DPD) is a well-established signal processing method that mitigates non-linearities of a PA when operated near saturation. Given the high PA count in MIMO systems, careful consideration must be taken to reduce the power consumption of the whole system, in order to ensure a satisfactory system efficiency. This would mean DPD power consumption for each transmission chain must be reduced. Apart from that, larger transmission bandwidths in next generation networks require high hardware processing rates in the order of a few GHz. Current hardware can satisfy up to hundreds of MHz processing rates. Thus, there is a need for parallelized signal processing methods in order to meet bandwidth requirements of 5G NR. This thesis aims to investigates and address a few challenges of deploying massive MIMO systems by designing and building a re-configurable DSP platform that allows implementation and validation for DSP algorithms including DPD, for real-time fully digital massive MIMO transceivers. This platform allows transmission of up to 16 fully digital channels at sub-6 GHz frequencies and supports up to 400 MHz of modulated bandwidths. Finally, a low-complexity and parallelized DPD solution is proposed and realized with a commercially available field-programmable-gate-array (FPGA).