Candidate: Mohammad Nouri
Title: Effect of microfabrication process on the electrical behavior of transition-metal dichalcogenide field-effect transistor arrays
Date: April 14, 2023
Time: 1:00 PM
Place: EIT 3142
Supervisor(s): Wong, William
Abstract:
The application of two-dimensional (2-D) layered transition metal dichalcogenide (TMDC) for high-performance large-area memory applications requires establishing long-term electrical stability through an understanding of the carrier transport and the effect of the materials processing on the device behavior. In this Ph.D. dissertation, a novel approach for creating arrays of thin-film and few-layer molybdenum disulfide (MoS2)-based field-effect transistors is developed through a mechanical exfoliation and a dry etching process. Few-layer structures (~ 3 monolayers) were fabricated using a dry etching process to thin multilayer (~ 60-90 nm thick) TMDC structures. Then, the effect of plasma etching of the TFT backchannel surface and bulk defects in the layers on the electrical performance and stability of the n-channel depletion-mode TFTs were investigated. The etching improved the threshold voltage of the TFTs, resulting in a positive threshold voltage shift of +40 Volts after etching the back channel, correlating to a bulk trap density of approximately 1×1016 cm-3eV-1 per monolayer. Etching the MoS2 surface resulted in a threshold voltage shift of 0.2 V per nanometer of MoS2 removed (for MoS2 thicknesses >15nm). For etched MoS2 layers reduced to < 15 nm, a threshold voltage change of ~1.8 V per nanometer was measured. The backchannel surface was also found to be doped and roughen due to the dry etching process but did not significantly affect the device performance until the MoS2 thickness was below 15 nm. An observed degradation of the carrier transport and electrical stability of these samples were found to be due to the proximity of the etched surface approaching the active channel region of the device. The results reveal the performance tradeoffs of fabricating large-area arrays of few-layer TMDC TFTs using a mechanical exfoliation and dry etching approach.
Hydrogen-contained passivation layers were then used to mitigate the impact of the surface defects on the TFT's electrical performance. It is discovered that the diffusion of the hydrogen into the active region of the TMDC devices after the passivation process causes n-type doping, leading to a degradation in the electrical performance and stability of the devices and a negative threshold voltage shift. Furthermore, it is shown that hydrogen diffusion has a higher impact on the electrical performance of TMDC devices with thicknesses less than 15 nm due to the hydrogen diffusion length. Therefore, a hydrogen barrier layer was used to reduce the adverse effect of hydrogen-containing backchannel passivation layers and processes. This approach might be used to make hydrogen-contained passivation layers more compatible with the TMDC semiconductors for developing the next generation of TMDC-based memory devices.
Finally, dual-gate TMDC-based TFT arrays were fabricated using a bilayer dielectric on pristine and backchannel etched TMDC films. The electrical characterization shows that the dual-gate TFTs suffered due to trap states on the backchannel surface of the etched TMDC-based TFTs. The research also revealed that the effectiveness of the top-gate electric field in regulating the electrical performance and stability of dual-gate TFTs is affected by both the presence of backchannel surface traps and the distance between the top gate and the active channel region. The findings of this study demonstrate that using a dual-gate structure is a feasible method for managing and adjusting the electrical performance and stability of TMDC-based TFTs affected by backchannel surface states.