Candidate:
Kleber
Hugo
Stangherlin
Title:
Secure
and
Unclonable
Integrated
Circuits
Date:
September
22,
2022
Time:
9:00
AM
Place:
REMOTE
ATTENDANCE
Supervisor:
Sachdev,
Manoj
Abstract:
Semiconductor
manufacturing
is
increasingly
reliant
in
offshore
foundries,
which
has
raised
concerns
with
counterfeiting,
piracy,
and
unauthorized
overproduction
by
the
contract
foundry.
The
recent
shortage
of
semiconductors
has
aggravated
such
problems,
with
the
electronic
components
market
being
flooded
by
recycled,
remarked,
or
even
out-of-spec,
and
defective
parts.
Moreover,
modern
internet
connected
applications
require
mechanisms
that
enable
secure
communication,
which
must
be
protected
by
security
counter-measures
to
mitigate
various
types
of
attacks.
In
this
thesis,
we
describe
techniques
to
aid
counterfeit
prevention,
and
mitigate
secret
extraction
attacks
that
exploit
power
consumption
information.
Counterfeit
prevention
requires
simple
and
trustworthy
identification.
Physical
unclonable
functions
(PUFs)
harvest
process
variation
to
create
a
unique
and
unclonable
digital
fingerprint
of
an
IC.
However,
learning
attacks
can
model
the
PUF
behavior,
invalidating
its
unclonability
claims.
In
this
thesis,
we
research
circuits
and
architectures
to
make
PUFs
more
resilient
to
learning
attacks.
First,
we
propose
the
concept
of
non-monotonic
response
quantization,
where
responses
not
always
encode
the
best
performing
circuit
structure.
Then,
we
explore
the
design
space
of
PUF
compositions,
assessing
the
trade-off
between
stability
and
resilience
to
learning
attacks.
Finally,
we
introduce
a
lightweight
key
based
challenge
obfuscation
technique
that
uses
a
chip
unique
secret
to
construct
PUFs
which
are
more
resilient
to
learning
attacks.
Modern
internet
protocols
demand
message
integrity,
confidentiality,
and
(often)
non-repudiation.
Adding
support
for
such
mechanisms
requires
on-chip
storage
of
a
secret
key.
Even
if
the
key
is
produced
by
a
PUF,
it
will
be
subject
to
key
extraction
attacks
that
use
power
consumption
information.
Secure
integrated
circuits
must
address
power
analysis
attacks
with
appropriate
counter-measures.
Traditional
mitigation
techniques
have
limited
scope
of
protection,
and
impose
several
restrictions
on
how
sensitive
data
must
be
manipulated.
We
demonstrate
a
bit-serial
RISC-V
microprocessor
implementation
with
no
plain-text
data,
where
all
values
are
protected
using
Boolean
masking
and
differential
domino
logic.
Software
can
run
with
little
to
no
counter-measures,
reducing
code
size
and
performance
overheads.
Our
methodology
is
fully
automated
and
can
be
applied
to
designs
of
arbitrary
size
or
complexity.
We
also
provide
details
on
other
key
components
such
as
clock
randomizer,
memory
protection,
and
random
number
generator.
Thursday, September 22, 2022 9:00 am
-
9:00 am
EDT (GMT -04:00)