Tuesday, March 29, 2016 — 10:00 AM EDT

Candidate

Yaoqiang Li

Title

An Energy-Efficient System with Timing-Reliable Error Detection Sequentials

Supervisor

Manoj Sachdev

Abstract

Energy-efficient digital systems have been previously developed to deploy Error Detection Sequential (EDS) circuits to detect the timing variations in data-paths due to Process, Voltage and Temperature (PVT) variations and adjust the supply voltage to a proper lower level so as to achieve energy efficiency. Nevertheless, the timing-reliability (including synchronization metastability and detection accuracy) of the EDS circuits, which is usually at the expense of circuit penalties such as design complexity, energy consumption and area cost, is the key to the systematic reliability.

In this work, Voltage-Boosted Synchronizers (VBSs) as the key component of EDS circuits are proposed to improve the intrinsic characteristic, the metastability behavior (reliability and latency) of the EDS circuits under single low-voltage supply environments. A new methodology for deploying the EDS circuits has been developed to enhance the extrinsic characteristic of EDS circuits, the detection accuracy. An FPGA-based Discrete Cosine Transform (DCT) system with the EDS and voltage control circuits deployed in the proposed method is implemented and demonstrates reliable operations and significant energy efficiency. By designing and deploying timing-reliable EDS circuits, our work significantly improve the reliability of the energy-efficient digital systems under various circumstances.

Location 
EIT building
Room 3142

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