PhD Seminar: Comprehensive analysis of physical unclonable functions on FPGAs: Implementation, attacks, and countermeasuresExport this event to calendar

Wednesday, August 29, 2018 — 9:00 AM EDT

Candidate: Mahmoud Khalafalla

Title: Comprehensive analysis of physical unclonable functions on FPGAs: Implementation, attacks, and countermeasures

Date: August 29, 2018

Time: 9:00 AM

Place: EIT 3141

Supervisor(s): Gebotys, Catherine H.

Abstract:

For more than a decade, Physical Unclonable functions (PUFs) have been presented as a promising hardware security primitive to provide a cheaper and more secure solution. The idea of exploiting variabilities in hardware fabrication to generate a unique fingerprint for every silicon chip introduced a more secure and cheaper alternative. Other solutions using non-volatile memory to store cryptographic keys, require additional processing steps to generate keys externally, and secure environments to exchange generated keys, which introduce many points of attack that can be used to extract the secret keys.

Previous research focused on proposing new PUF architectures to improve security properties like response uniqueness per chip, response reproducibility of the same PUF input, and response unpredictability using previous input/response pairs. Moreover, attack schemes were proposed to clone the response of PUFs, using conventional machine learning (ML) algorithms, side channel attacks using power and electromagnetic traces, and fault injection using laser beams and electromagnetic pulses. However, most attack schemes to be successful, imposed some restrictions on targeted PUF architectures, which make it simpler and easier to attack. Furthermore, they did not propose solid and provable enhancements on these architectures to countermeasure the attacks.

This PhD research contributes to state-of-the-art research on physical unclonable functions by providing a comprehensive analysis of the implementation of secure PUFs on FPGAs using manual placement and manual routing techniques guided by new performance metrics to overcome FPGAs restrictions with minimum hardware and area overhead. Then studying the use of deep learning algorithms as promising attack schemes against complex PUFs architectures to overcome the restrictions imposed by previous research.

Obtained results showed that manual routing techniques conducted in our experiments could increase PUFs resistance against modeling attacks. However, inherent architectural properties allow modeling attacks to be successful, which requires different designs from architectural perspective. Furthermore, modeling attacks using deep learning showed promising results against PUF architectures which showed strong resistance against conventional models in previous research. Finally, future research will complete this comprehensive analysis by investigating new PUF architectures and extra circuitry to thwart proposed attacks and provide attack detection and prevention mechanisms

Location 
EIT - Centre for Environmental and Information Technology
Room 3141
200 University Avenue West

Waterloo, ON N2L 3G1
Canada

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