Candidate: Hang Yu
Date: April 1, 2026
Time: 4:00 PM
Location: Online
Supervisor: Slim Boumaiza
All are welcome!
Abstract:
This Ph.D. seminar addresses the hardware challenges of 5G and 6G infrastructure, specifically focusing on high-frequency integration, energy efficiency under high PAPR signals, and robustness against dynamic load variations in Multiple-Input-Multiple-Output (MIMO) architectures. The research presents three primary objectives that bridge the gap between theoretical load-insensitivity and practical circuit synthesis. To enhance circuit integration for 39 GHz TDD operation, the work first introduces a switchless Transmit/Receive (T/R) Front-End Module (FEM) in 45nm SOI CMOS that utilizes a Doherty Power Amplifier (DPA) as a dual-purpose isolation network, effectively reducing area and insertion loss.
The presentation then details the mitigation of antenna mutual coupling in large-scale arrays through a dual-mode 28 GHz PA design in 22nm FD-SOI. This architecture reconfigures between a VSWR-resiliency mode for mismatched loads and an efficiency-enhancement mode for optimized back-off performance. Finally, the seminar concludes by unifying these requirements into a generalized design framework for a "VSWR-Resilient DPA." This proposed theory establishes a strategy to simultaneously maintain high average efficiency and the necessary load-variation resiliency. The feasibility of this unified approach is demonstrated through comprehensive simulations of an 8 GHz prototype realized with a commercial GaN bare-die transistor on a multi-layer PCB substrate.