PhD Seminar Notice: Low-power and Radiation Hardened TSPC Registers

Wednesday, July 24, 2024 1:00 pm - 2:00 pm EDT (GMT -04:00)

Candidate: Yugal Kishore Maheshwari

Title: Low-power and Radiation Hardened TSPC Registers

Date: July 24, 2024

Time: 1:00 PM

Place: REMOTE ATTENDANCE

Supervisor(s): Sachdev, Manoj

All are welcome!

Abstract:

Battery operated systems require power and energy-efficient circuits to extend their battery life. Flip-flops are basic component of digital circuits and their power consumption and speed significantly impact the overall performance of a digital system. A clock network in a complex System on a Chip (SoC) consumes a substantial amount of power. Additionally, often pipelines are used to enhance the system throughput which puts additional burden on the clock network. Arguably, a flip-flop with fewer clock transistors will reduce its power burden on the clock network. This research proposes three very low-power flip-flops with only two and three single-phase clock transistors. Moreover, scan-chain of 256 flip-flops and advanced encryption engine (AES-128) are implemented as a benchmark to further investigate the power savings of the proposed flip-flops.

Furthermore, high-performance computations in integrated circuits (ICs) are increasingly needed for space applications. ICs are subjected to high-energy ionizing particles in the radiant space environment which will cause the device performance to degrade or even fail. A single even upset (SEU), occurs in the logic circuit when an ion strikes a device's sensitive node, changing the output from 0 to 1 or 1 to 0. In radiant applications, ICs contain storage cells like flip-flops, latches, or RAMs, and always experience SEU. Although package and process engineering can minimize alpha particles, cosmic neutrons cannot be physically blocked. Therefore, for high reliability systems, soft-error tolerant circuit designs are crucial. Traditional radiation hardened by design (RHBD) techniques have some trade-offs between area, speed, power and energy consumption. Thus, new designs are required to reduce these penalties. This research proposes high-performance, low-power, low-energy, and low-area flip-flop suitable for space applications.