Wednesday, June 3, 2015 — 1:30 PM EDT

Candidate

Shahin Solki

Title

Voltage-variation aware multi-mode timing closure of high-performance cores

Supervisor

Manoj Sachdev

Abstract

In high-performance cores such as GPUs and CPUs, it is essential to support a wide operating voltage and temperature range, which pose a design challenge, and often leads to power, performance or silicon area penalties. In this talk, the analysis results of critical and near critical paths extracted from a SIMD-based GPU and 64-bit ARM core are provided to discuss their voltage scalability and temperature sensitivity. A set of metrics are introduced to determine design weak points and methods to improve them. Furthermore to optimize the solution, a voltage-variation aware timing methodology is described to determine effective path-based jitter margin instead of a global setting. It is accomplished by analysing voltage noise impact on clock skew, slack and path delay. The average and effective voltage are introduced as metrics to quantify voltage droop impact on the circuit timing.

Location 
EIT building
Room 3142

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