PhD Seminar: Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS TechnologiesExport this event to calendar

Thursday, December 7, 2017 — 11:00 AM EST

Candidate: Morteza Nabavi

Title: Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS Technologies

Date: December 7, 2017

Time: 11:00 AM

Place: E5 4047

Supervisor(s): Sachdev, Manoj

Abstract:

Embedded SRAM circuits are vital components in the modern system on chips (SOCs) that can occupy up to 90% of the total area. Therefore, SRAM circuits heavily affect SOC’s performance, energy consumption, reliability, and yield. The aggressive demand in portable devices and billions of connected sensor networks requires long battery life. Therefore, careful design of SRAM circuits with minimal power consumption is highly demanded. Reducing the power consumption is mainly achieved by reducing the power supply voltage in the idle mode. However, simply reducing the supply voltage imposes practical limitations on SRAM circuits such as reduced static noise margin, poor write margin, reduced number of cells per bitline, and reduced bitline sensing margin that might cause read/write failures. In addition, SRAM bitcell has contradicting requirements for read stability and writability. Improving the read stability can cause difficulties in a write operation or vice versa.

In this thesis, various techniques to design subthreshold energy efficient SRAM circuits are proposed. The techniques proposed include improvement in read margin and write margin, speed improvement, energy consumption reduction, new bitcell architecture and utilizing programmable wordline boosting. A programmable wordline boosting technique is exploited on a conventional 6T SRAM bitcell to improve the operational speed. In addition, wordline boosting can reduce the supply voltage while maintaining the operational frequency. The reduction of the supply voltage allows the memory macro to operate at a reduced level of energy and power consumption. To verify the design, a 16-kb SRAM is fabricated using the TSMC 65 nm CMOS technology. Measurement results show that the maximum operational frequency increases up to 33.3% when wordline boosting is applied. Besides, the supply voltage can be reduced while maintaining the same frequency. This allows reducing the energy consumption by 22.2%. The minimum energy consumption achieved is 0.536 fJ/b at 400 mV. Moreover, to improve the read margin, a 6T bitcell SRAM with PMOS access transistor is proposed. Utilizing PMOS access transistor results in lower zero level degradation, hence higher read stability. In addition, the access transistor connected to the internal node holding VDD acts as a stabilizer and counterbalances the effect of zero level degradation. In order to improve the writability, wordline boosting is exploited. Wordline boosting also helps to compensate the lower speed of the PMOS access transistor compared to NMOS transistor. To verify our design, a 2kb SRAM is fabricated in the TSMC 65 nm CMOS technology. Measurement results show that the maximum operating frequency of the test chip is at 3.34 MHz at 290 mV. The minimum energy consumption is measured as 1.1 fJ/b at 400 mV.

Location 
Engineering 5
Room 4047
200 University Avenue West

Kitchener, ON N2L 3G1
Canada

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