Speaker
Professor Brett H. Meyer, McGill University, Canada
Topic
Managing Multicore Power Integrity and Voltage Noise via Walking Pads C4 Placement
Abstract
While CMOS technology scaling has resulted in exponentially greater transistor densities, threshold and supply voltages no longer decrease fast enough to prevent exponential growth in on-chip power and current density. As a result, delivering a stable voltage supply to switching transistors is increasingly challenging. Furthermore, competition for limited chip interface resources (i.e., C4 pads) between power supply and I/O, and the loss of such resources to electro-migration, means that constructing a power delivery network (PDN) that satisfies noise margins without compromising performance is and will remain a critical problem for architects and circuit designers alike. Simple guard-banding will no longer suffice, as the consequent performance penalty will grow with technology scaling. To assist designers with mitigating power supply noise, we propose a novel C4 pad placement optimization framework for 2D power delivery grids: Walking Pads (WP). WP is built on top of the VoltSpot power-delivery network (PDN) modeling framework, consisting of multi-core architectural performance, power, and physical design tools for performing detailed PDN analysis. In this context, WP optimizes pad locations by moving pads according to the “virtual forces” exerted on them by other pads and current sources in the system. We have studied WP algorithms in the context of both steady-state IR drop and transient dI/dt voltage noise, and observe that WP implementations (a) outperform existing techniques by two orders of magnitude, (b) enable the rapid exploration of the design space (in the case of steady-state IR drop), and (c) represent the only approach to pad placement for transient dI/dt voltage noise minimization.
Speaker's biography
Brett H. Meyer is a Chwang-Seto Faculty Scholar and assistant professor in the Department of ECE at McGill University. He received his MS and PhD in Electrical and Computer Engineering from Carnegie Mellon University in 2005 and 2009, respectively. He received his BS in Electrical Engineering, Computer Science and Math from the University of Wisconsin-Madison in 2003. After receiving his PhD, Meyer worked as a post-doctoral research associate in the Computer Science Department at the University of Virginia. He has been on the faculty at McGill since 2011. Meyer’s research interests are focused on the design and architecture of resilient multiprocessor computer systems. Meyer’s research has been recognized with Best Paper in Session awards at SRC TECHCON (2007 and 2013), and a nomination for Best Paper at ASPDAC 2014 and GLSVLSI 2015.
Invited by Professor Hiren Patel