Design of Low Voltage Unsaturated Ring Oscillator for a Sigma Delta Time to Digital Converter
This thesis investigates the phase noise of two 2-stage cross-coupled pair unsaturated ring oscillators with no tail current source. One oscillator consists of top cross-coupled pair delay cells, and the other consists of top cross-coupled pair and bottom cross-coupled pair delay cells. Under a low supply voltage restriction, a phase noise model is developed and applied to both ring oscillators. Both top cross-coupled pair and top and bottom cross-coupled pair oscillators are fabricated with 0.13 um CMOS technology. Phase noise measurements of -92dBc/Hz and -89dBc/Hz, respectively, at 1Mhz offset is obtained from the chip, which agree with theory and simulations. Top cross-coupled ring oscillator, with phase noise of -92dBc/Hz at 1Mhz offset, is implemented in a second order sigma-delta time to digital converter. System level and transistor level functional simulation and timing jitter simulation are obtained.
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