Worst-Case Latency Analysis for the Versal Network-on-Chip

Candidate: Ian Elmor Lang
Title: Worst-Case Latency Analysis for the Versal Network-on-Chip
Date: December 16, 2021
Time: 15:00
Place: online
Supervisor(s): Kapre, Nachiket - Pellizzoni, Rodolfo

Abstract:
The recent line of Versal FPGA devices from Xilinx Inc. includes a hard NetworkOn-Chip (NoC) embedded in the programmable logic,
designed to be a high-performance system-level interconnect. While the target markets for Versal devices include applications
with real-time constraints, such as automotive driver assist, the associated development tools only provide figures for
”structural latencies” of data packets, which assume that the
network is otherwise idle. In a realistic setting, this information is not enough to ensure deadlines are met, as different
packets can contend for NoC switch outputs, which causes packet contents to be buffered while in transit, increasing their
latency. In this work, we develop an approach for calculating upper bounds for such worst-case latencies (WCLs), assuming a model
where system tasks release packets into the NoC periodically. In order to develop an accurate model for latencies in the network,
we review the architecture and operation of the Versal NoC. We focus on a formal description of the NPS switches that compose the
NoC from a flit arbitration perspective, based on study the available cycle-accurate switch simulation code. Working with the
presented model, we propose an adaptation to an existing approach for WCL analysis in NoC, Recursive Calculus (RC), in order to
apply it to the arbitration policy implemented in the Versal NoC. To evaluate the
proposed approach, we implement a simulation experiment for the Versal NoC, with custom endpoints that allow for injecting
packets programatically and measuring their latencies over the NoC. We simulate both a single NPS module and a complete NoC
routing periodic workloads, in order to compare with the values given by the WCL approach and identify sources of pessimism.