Lan Wei

Lan Wei
Associate Professor
Location: E5 4023
Phone: 519-888-4567 x31423

Biography

Professor Lan Wei received her B.S. in Microelectronics and Economics from Peking University, Beijing, China in 2005 and M.S. and Ph.D. in Electrical Engineering from Stanford University, Stanford, USA (with Professor H.–S. Philip Wong) in 2007 and 2010, respectively. Before joining University of Waterloo in 2014, she worked at Altera Corporation in San Jose, California, where her responsibilities included foundary technology evaluation, power management and Stratix X FPGA product development with Intel 14nm technology. She also worked as a post-doctoral associate in Microsystems Technology Laboratories, Massachusetts Institute of Technology under Professor Dimitri Antoniadis. Her research focuses on device-circuit interactive design and optimization, cryogenic CMOS electronics for quantum computing, error-resilient computation, and integrated electronic systems using emerging technologies including GaN, RRAM and low-dimensional materials.

Wei has served on the Technical Program Committee of several academic conferences including IEDM (2011-2012, 2021-2022), DATE (2021 - ), ICCAD (2019 - ), VLSI-TSA (2013 - ), GLSVLSI (2017 - ), ISQED (2019 - ) ISLPED (2013), etc, and was listed as one of the key contributors to the Process Integration, Devices, and Structures Chapter (PIDS) of International Technology Roadmap for Semiconductors (ITRS) 2009 Edition. She is the co-developer of the MIT Virtual Source GaN HEMT (MVSG) Compact Model, which is an Industry Standard approved and supported by the Compact Model Coalition for GaN HEMT compact model.

Research Interests

  • Nanoelectronic devices
  • Device-circuit interactive design and optimization
  • Cryogenic CMOS electronics for quantum computing
  • GaN-based devices and circuits
  • Low-dimensional materials based integrated nanoelectronic systems
  • RRAM device, circuit, and integrated system
  • Device-circuit interactive design
  • Error-resilient computing

Industrial Research

Prof. Wei's group is responsible for MIT virtuall-source Galliuam-nitride field effect transistor (MVSG) compact model, which is an industry-standard GaN FET compact model used globally. The latest publicly available MVSG model can be downloaded through Compact Model Coalition ([https://si2.org/standard-models/](https://si2.org/standard-models/)).

Education

  • 2010, Ph.D., Electrical Engineering, Stanford University, U.S.A.
  • 2007, Master of Science, Electrical Engineering, Stanford University, U.S.A.
  • 2005, Bachelor of Science, Microelectronics and Economics, Peking University, China

Awards

  • 2019 Ontario Early Researcher Award
  • 2020 UWaterloo President's Excellence Award in Research

Teaching*

  • ECE 240 - Electronic Circuits 1
    • Taught in 2021, 2022, 2023
  • ECE 445 - Integrated Digital Electronics
    • Taught in 2021, 2022
  • ECE 730 - Special Topics in Solid State Devices
    • Taught in 2019, 2021
  • MTE 481 - Mechatronics Engineering Design Project
    • Taught in 2022

* Only courses taught in the past 5 years are displayed.

Selected/Recent Publications

  • Y. Shen, X. S. Chen*, Y. -C. Hua, H. -L. Li, L. Wei and B. -Y. Cao, "Bias Dependence of Non-Fourier Heat Spreading in GaN HEMTs," in IEEE Transactions on Electron Devices, No. 12, 2022.
  • S. Wang, C. Xu, M. C. Tam, K. Vaillancourt, Z. Wasilewski, L. Wei, and D. Ban, "Visualization of localized facet Joule heating induced optical degradation on mid-infrared quantum cascade lasers," Opt. Express 30, 43342-43353 (2022)
  • T. Guo, K. Pan*, Y. Jiao*, B. Sun, C. Du, J. P. Mills, Z. Chen, X. Zhao, L. Wei, Y. N. Zhou, and Y. Wul. "Versatile memristor for memory and neuromorphic computing." Nanoscale Horizons 7, no. 3 (2022): 299-310.
  • Z. Yang*, K. Pan*, N. Zhou, and L. Wei, “Scalable 2T2R Logic Computation Structure: Design from Digital Logic Circuits to 3-D Stacked Memory Arrays,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 8, no. 2, pp. 84-92, Dec. 2022.
  • H. H. Yang, M. Robitaille, X. Chen*, H. Elgabra*, L. Wei and N. Y. Kim, "Random Telegraph Noise of a 28-nm Cryogenic MOSFET in the Coulomb Blockade Regime," in IEEE Electron Device Letters, vol. 43, no. 1, pp. 5-8, Jan. 2022. (Yang, Robitaille and Chen have equal contributions.)
  • B. Sun; S. Ranjan*, G. Zhou, T. Guo, C. Du, L. Wei, Y. N. Zhou, Y. Wu, “A True Random Number Generator Based on Ionic Liquid Modulated Memristors,” ACS Applied Electronic Materials, vol. 3, no. 5, pp 2380-2388, 2021.
  • B. Sun, S. Ranjan*, G. Zhou, T. Guo, Y. Xia, L. Wei, Y.N. Zhou, Y.A. Wu, “Multistate Resistive Switching Behaviors for Neuromorphic Computing in Memristor,” Materials Today Advances, vol. 9, pp 1-8, 2021.
  • R. Fang*, Y. Feng*, J. Chong*, K. Chan, U. Radhakrishna, L. Wei, “Comprehensive MVSG Compact Model for Power GaN Devices,” accepted by 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2023.
  • R. Absar*, Z.D. Merino, H. Elgabra*, X. Chen, J. Baugh, L Wei, “Scalable Addressing Circuits for a Surface Code Quantum Computer in Silicon,” 2022 IEEE/ACM International Symposium on Nanoscale Architectures, Dec 2022.
  • Y. Zhao*¬, Y. Yoon, L. Wei, “A Multi-Level Simulation of GeH FETs: From Nanomaterial and Device Characteristics to Circuit Performance Optimization,” 2022 IEEE/ACM International Symposium on Nanoscale Architectures, Dec 2022.
  • R. Fang*, D. Ma*, U. Radhakrishna, and L. Wei, “MVSG GaN-HEMT Model: Approach to Simulate Fringing Field Capacitances, Gate Current De-biasing, and Charge Trapping Effects,” 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, Phoenix, USA, Oct 2022 (Best Student Paper Award)
  • P. Choi, R. Fang*, L. Wei, S. Boumaiza, U. Radhakrishna, and E. Fitzgerald, “Design of 20-28 GHz GaAs Phase Shifter MMIC and Small Signal Validation using MVSGaAs Model,” 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, Phoenix, USA, Oct 2022
  • R. Absar*, Z.D. Merino, H. Elgabra*, X. Chen, J. Baugh, L Wei, “Scalable Addressing Circuits for a Surface Code Quantum Computer in Silicon,” 2022 Silicon Quantum Electronics Workshop, Orford, Quebec, Canada, Oct 2022.
  • H. Elgabra*, F. Sfigakis, R. Absar*, X. Chen, J. Baugh, L Wei, “Cryogenic Virtual Source I-V Model for MOSFET Devices,” 2022 Silicon Quantum Electronics Workshop, Orford, Quebec, Canada, Oct 2022.
  • K. Pan*, A. Tosson, N. Wang*, N. Y. Zhou and L. Wei, “A Novel RRAM and CR-based TCAM Design for High-speed and Energy-efficient Applications,” IEEE/ACM Great Lakes Symposium on VLSI, May 2022.

Graduate studies