Assistant Professor

Contact InformationLan Wei

Website

Biography Summary

Professor Lan Wei received her B.S. in Microelectronics and Economics from Peking University, Beijing, China in 2005 and M.S. and Ph.D. in Electrical Engineering from Stanford University, Stanford, USA (with Professor H.–S. Philip Wong) in 2007 and 2010, respectively. Before joining University of Waterloo in 2014, she worked at Altera Corporation in San Jose, California, where her responsibilities included foundary technology evaluation, power management and Stratix X FPGA product development with Intel 14nm technology. She also worked as a post-doctoral associate in Microsystems Technology Laboratories, Massachusetts Institute of Technology under Professor Dimitri Antoniadis. Her research focuses on device-circuit interactive design and optimization, cryogenic CMOS electronics for quantum computing, error-resilient computation, and integrated electronic systems using emerging technologies including GaN, RRAM and low-dimensional materials.

Wei has served on the Technical Program Committee of several academic conferences including IEDM (2011-2012, 2021-2022), ICCAD (2019 - ), VLSI-TSA (2013 - ), GLSVLSI (2017 - ), ISQED (2019 - ) ISLPED (2013), etc, and was listed as one of the key contributors to the Process Integration, Devices, and Structures Chapter (PIDS) of International Technology Roadmap for Semiconductors (ITRS) 2009 Edition. She is the co-developer of the MIT Virtual Source GaN HEMT (MVSG) Compact Model, which is an Industry Standard approved and supported by the Compact Model Coalition for GaN HEMT compact model.

Research Interests

  • Nanoelectronic devices
  • Device-circuit interactive design and optimization
  • Cryogenic CMOS electronics for quantum computing
  • GaN-based devices and circuits
  • Low-dimensional materials based integrated nanoelectronic systems
  • RRAM device, circuit, and integrated system
  • Device-circuit interactive design
  • Error-resilient computing

Education

  • 2010, Doctorate, Electrical Engineering, Stanford University
  • 2007, Master of Applied Science, Electrical Engineering, Stanford University
  • 2005, Bachelor of Science (BS), Microelectronics and Economics, Peking University

Courses*

  • ECE 240 - Electronic Circuits 1
    • Taught in 2016, 2018
  • ECE 445 - Integrated Digital Electronics
    • Taught in 2017, 2018
  • ECE 499 - Engineering Project
    • Taught in 2016, 2017
  • ECE 730 - Topics in Solid State Devices
    • Taught in 2017, 2019
* Only courses taught in the past 5 years are displayed.

Selected/Recent Publications

  • Sun, B and Ranjan, S and Zhou, G and Guo, T and Xia, Y and Wei, L and Zhou, YN and Wu, YA, Multistate resistive switching behaviors for neuromorphic computing in memristor, Materials Today Advances, 9, 2021
  • Chen, Xuesong and Boumaiza, Slim and Wei, Lan, Modeling Bias Dependence of Self-Heating in GaN HEMTs Using Two Heat Sources, IEEE Transactions on Electron Devices, 67(8), 2020, 3082 - 3087
  • Ranjan, Shubham and Sun, Bai and Zhou, Guangdong and Wu, Yimin A and Wei, Lan and Zhou, Norman Y, Passive Filters for Nonvolatile Storage Based on Capacitive-Coupled Memristive Effects in Nanolayered Organic-Inorganic Heterojunction Devices, ACS Applied Nano Materials, 2020
  • Guo, Tao and Sun, Bai and Ranjan, Shubham and Jiao, Yixuan and Wei, Lan and Zhou, Y Norman and Wu, Yimin A, From Memristive Materials to Neural Networks, ACS Applied Materials & Interfaces, 2020
  • Chen, Xuesong and Boumaiza, Slim and Wei, Lan, Self-heating and equivalent channel temperature in short gate length GaN HEMTs, IEEE Transactions on Electron Devices, 66(9), 2019, 3748 - 3755

Graduate Studies