Lan Wei

Professor Lan Wei received her B.S. in Microelectronics and Economics from Peking University, Beijing, China in 2005 and M.S. and Ph.D. in Electrical Engineering from Stanford University, Stanford, USA (with Professor H.–S. Philip Wong) in 2007 and 2010, respectively. Before joining University of Waterloo in 2014, she worked at Altera Corproation in San Jose, California, where her responsibilities included foundary technology evaluation, power management and Stratix X FPGA product development with Intel 14nm technology. She also worked as a post-doctoral associate in Microsystems Technology Laboratories, Massachusetts Institute of Technology under Professor Dimitri Antoniadis. Her research focuses on device-circuit interactive design and optimization, integrated nanoelectronic systems with low-dimensional materials, as well as GaN-based technology.

Wei has served on the Technical Program Committee of IEDM (2011-2012), ISLPED (2013), VSLI-TSA (2013), CCECE (2014), IEEE-NANO (2014), and was listed as one of the key contributors to the PIDS (Process Integration, Devices, and Structures) Chapter of ITRS (International Technology Roadmap for Semiconductors) 2009 Edition.

• Nanoelectronic devices
• GaN-based devices and circuits
• Integrated systems
• Device-circuit interactive design and optimization
• Low-dimensional materials based integrated Nanoelectronic systems
• Nanotechnology

• 2010, Doctorate, Electrical Engineering, Stanford University
• 2007, Master of Applied Science, Electrical Engineering, Stanford University
• 2005, Bachelor of Science (BS), Microelectronics and Economics, Peking University

• ECE 140 - Linear Circuits
  • Taught in 2014
• ECE 499 - Engineering Project
  • Taught in 2014, 2015, 2016, 2017
• ECE 730 - Special Topics in Solid State Devices
  • Taught in 2014, 2017
• ECE 445 - Integrated Digital Electronics
  • Taught in 2017, 2018
• ECE 240 - Electronic Circuits 1
  • Taught in 2015, 2016, 2018

• Zhang, Hao and Gupta, Mayank and Watt, Jeff and Wei, Lan, Effective Drive Current for Pass-Gate Transistors, , 2016
• Regner, KT and Wei, LC and Malen, JA, Interpretation of thermoreflectance measurements with a two-temperature model including non-surface heat deposition, Journal of Applied Physics, 118(23), 2015
• Jiang, Xiaobo and Wang, Junyao and Wang, Xingsheng and Wang, Runsheng and Cheng, Binjie and Asenov, Asen and Wei, Lan and Huang, Ru, New assessment methodology based on energy--delay--yield cooptimization for nanoscale CMOS technology, IEEE Transactions on Electron Devices, 62(6), 2015, 1746 - 1753
• Luo, Jieying and Wei, Lan and Lee, Chi-Shuen and Franklin, Aaron D and Guan, Ximeng and Pop, Eric and Antoniadis, Dimitri A and Wong, H-S Philip, Compact model for carbon nanotube field-effect transistors including nonidealities and calibrated with experimental data down to 9-nm gate length, IEEE Transactions on Electron Devices, 60(6), 2013, 1834 - 1843
• Zhang, Jie and Lin, Albert and Patil, Nishant and Wei, Hai and Wei, Lan and Wong, HS and Mitra, Subhasish, Robust digital VLSI using carbon nanotubes, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(4), 2012, 453 - 471